What Is a Control Register?

Control registers (CR0 to CR3) are used to control and determine the operating mode of the processor and the characteristics of the task currently being executed, as shown in Figure 4-3. CR0 contains the system control flags that control the operating mode and status of the processor; CR1 is reserved; CR2 contains the linear address that caused the page fault; CR3 contains the physical directory base address of the page directory table, so this register is also called the page directory base address Register PDBR (Page-Directory Base address Register).

Control registers (CR0 to CR3) are used to control and determine the operating mode of the processor and the characteristics of the task currently being executed, as shown in Figure 4-3. CR0 contains the system control flags that control the operating mode and status of the processor; CR1 is reserved; CR2 contains the linear address that caused the page fault; CR3 contains the physical directory base address of the page directory table, so this register is also called the page directory base address Register PDBR (Page-Directory Base address Register).

Chinese name

Control register

Field

Assembly language

CR0 Coprocessor control bit in control register CR0

The four bits of CR0: extended type bit ET, task switching bit TS, emulation bit EM, and mathematical existence bit MP are used to control the operation of the 80x86 floating-point (mathematics) coprocessor. The ET bit (flag) of CR0 is used to select the protocol used to communicate with the coprocessor, that is, to indicate whether the 80387 or 80287 coprocessor is used in the system. The TS, MP, and EM bits are used to determine whether a floating-point instruction or a WAIT instruction should generate a Device Not Available (DNA) exception. This exception can be used to save and restore floating-point registers only for tasks that use floating-point operations. For tasks that do not use floating-point arithmetic, doing so speeds up switching between them.

ET Control register ET

Bit 4 of CR0 is an Extension Type flag. When the flag is 1, it indicates that there are 80387 coprocessors in the system and the 32-bit coprocessor protocol is used. ET = 0 indicates the use of the 80287 coprocessor. If the emulation bit EM = 1, this bit is ignored. During a processor reset operation, the ET bit is initialized to indicate the type of coprocessor used in the system. If there is 80387 in the system, ET is set to 1, otherwise if there is an 80287 or no coprocessor, ET is set to 0.

TS Control register TS

Bit 3 of CR0 is the Task Switched flag. This flag is used to postpone saving the coprocessor content at the time of task switching until the new task starts actually executing coprocessor instructions. The processor sets this flag on every task switch and tests the flag when executing coprocessor instructions.

If the TS flag is set and CR0's EM flag is 0, a device-free exception will be generated before executing any coprocessor instructions. If the TS flag is set but the MP and EM flags of CR0 are not set, no device-free exception will be generated before executing the coprocessor instructions WAIT / FWAIT. If the EM flag is set, the TS flag has no effect on the execution of coprocessor instructions, see Table 4-1.

Table 4-1 Effect of different combinations of flags EM, MP and TS in CR0 on coprocessor instruction actions

Flags in CR0	Instruction type
EM	MP	TS	floating point	WAIT / FWAIT
0	0	0	carried out	carried out
0	0	1	Device does not exist (DNA) abnormal	carried out
0	1	0	carried out	carried out
0	1	1	DNA abnormalities	DNA abnormalities
1	0	0	DNA abnormalities	carried out
1	0	1	DNA abnormalities	carried out
1	1	0	DNA abnormalities	carried out
1	1	1	DNA abnormalities	DNA abnormalities

When the task is switched, the processor does not automatically save the coprocessor context, but instead sets the TS flag. This flag causes the processor to generate a device-free exception whenever it encounters a coprocessor instruction at any time during the execution of a new task instruction stream. A handler that does not have an exception on the device can use the CLTS instruction to clear the TS flag and save the coprocessor context. If the task has never used a coprocessor, the corresponding coprocessor context does not need to be saved.

EM Control register EM

Bit 2 of CR0 is the emulation (EMulation) flag. When this bit is set, it means that the processor does not have an internal or external coprocessor, and the execution of the coprocessor instructions will cause the device to have no exception; when cleared, it indicates that the system has a coprocessor. Setting this flag forces all floating-point instructions to be simulated in software.

MP Control register MP

Bit 1 of CR0 is the monitor coprocessor (Math Coprocessor or Math Present) flag. Used to control the interaction between the WAIT / FWAIT instruction and the TS flag. If MP = 1 and TS = 1, then the execution of the WAIT instruction will generate a device without exception; if MP = 0, the TS flag will not affect the execution of WAIT.

CR0 Protection control bit in control register CR0

PE Control register PE

Bit 0 of CR0 is the Protection Enable flag. When this bit is set, protection mode is turned on; when reset, it enters real address mode. This flag only enables segment-level protection and does not enable paging. To enable the paging mechanism, both the PE and PG flags are set.

PG Control register PG

Bit 31 of CR0 is the paging flag. When this bit is set, the paging mechanism is turned on; when resetting, the paging mechanism is disabled. At this time, all linear addresses are equivalent to physical addresses. The PE flag must be turned on before or at the same time. That is, to enable the paging mechanism, both the PE and PG flags must be set.

WP Control register WP

For Intel 80486 or above CPU, Bit 16 of CR0 is the Write Protect flag. When this flag is set, the processor will prohibit superuser programs (such as those with privilege level 0) from performing write operations to user-level read-only pages; the reverse is true when this bit is reset. This flag is beneficial for UNIX-like operating systems to implement Copy on Write technology when creating processes.

N Control register N

For Intel 80486 or above CPU, Bit 5 of CR0 is a Numeric Error flag. When this flag is set, the internal reporting mechanism for x87 coprocessor errors is enabled; if the flag is reset, the x87 coprocessor error reporting mechanism in the form of a PC is used. When NE is reset and there is a signal at the IGNNE input pin of the CPU, the math coprocessor x87 error will be ignored. When NE is in the reset state and there is no signal at the IGNNE input pin of the CPU, then the non-shielded math coprocessor x87 error will cause the processor to generate an external interrupt through the FERR pin and execute the next wait form floating point instruction Or immediately before the WAIT / FWAIT instruction. The FERR pin of the CPU is used to simulate the ERROR pin of the external coprocessor 80387, so it is usually connected to the interrupt controller input request pin. The NE flag, IGNNE pin, and FERR pin are used to implement external error reporting mechanisms in the form of a PC using external logic.

The protected mode PE (Protected Enable) bit (Bit 0) and the paging PG (Paging) bit (Bit 31) are used to control the segmentation and paging mechanisms, respectively. PE is used to control the segmentation mechanism. If PE = 1, the processor works in the environment of enabling the segmentation mechanism, that is, it runs in the protection mode. If PE = 0, the processor disables the segmentation mechanism and operates in real-address mode like the 8086. PG is used to control the paging mechanism. If PG = 1, the paging mechanism is turned on. If PG = 0, the paging mechanism is disabled, and the linear address is directly used as the physical address.

If PE = 0, PG = 0, the processor works in real address mode; if PG = 0, PE = 1, the processor works in protection mode without paging mechanism enabled; if PG = 1, PE = 0, this Since the paging mechanism cannot be enabled in the protection mode, the processor will generate a general protection exception, that is, this flag combination is invalid; if PG = 1, PE = 1, the processor works in the protection mode with the paging mechanism enabled .

Care must be taken when changing the PE and PG bits. We can only change the PG bit setting when at least part of the code and data of the executing program has the same address in the linear address space and the physical address space. This part of the code with the same address acts as a bridge between the paged and unpaged worlds. This part of the code has the same address regardless of whether the paging mechanism is turned on. In addition, the page cache TLB must be flushed before paging is turned on (PG = 1).

After the PE bit is modified, the program must immediately use a jump instruction to refresh the processor's execution of any instruction in a different mode that has been acquired in the pipeline. Before setting the PE bit, the program must initialize several system segments and control registers. When the system is powered on, the processor is reset to PE = 0 and PG = 0 (that is, real mode state) to allow the boot code to initialize these registers and data structures before enabling the segmentation and paging mechanisms.

CR2CR3 Control registers CR2 and CR3

CR2 and CR3 are used for paging mechanism. CR3 contains the physical address of the page directory table page, so CR3 is also called PDBR. Because the page directory table page is page-aligned, only the upper 20 bits of this register are valid. The lower 12 bits are reserved for higher-level processors, so the lower 12 bits must be set to 0 when loading a new value into CR3.

Using the MOV instruction to load CR3 has the side effect of invalidating the page cache. In order to reduce the number of bus cycles required for address translation, the page directories and page tables accessed in recent days are stored in the processor's page cache device, which is called the Translation Lookaside Buffer (TLB) ). Only when the required page table entries are not included in the TLB will additional page cycles be used to read page table entries from memory.

Even if the PG bit in CR0 is reset (PG = 0), we can load CR3 first. To allow the paging mechanism to be initialized. When switching tasks, the content of CR3 will also change accordingly. But if the CR3 value of the new task is the same as the original task, the processor does not need to refresh the page cache. This allows tasks that share page tables to execute faster.

CR2 is used to report an error message when a page exception occurs. When a page exception is reported, the processor stores the linear address that caused the exception in CR2. Therefore, the page exception handler in the operating system can determine which page in the linear address space caused the exception by examining the contents of CR2.