What Is Power Optimization?

Definition 1: Power loss refers to the difference between input power and output power of equipment and devices. ^[1] Power loss. Circuits usually refer to the thermal energy dissipated on the elements and devices.

[gng hào]

Definition 1: Power loss refers to the input power of equipment, devices, etc.

Pinyin: gnghào

English: power waste (correctly speaking, power consumption)

In 2001, the European Union required rating

Why do you need low power?

With the continuous development of SOC integration and performance, today's SOC has reached the order of hundreds of watts. For example, Intel's Itanium2 consumes about 130 watts, which requires expensive packaging, heat sinks and cooling environments. According to Moore's Law, transistor density doubles every 18 months, and it takes five years for power technology to reach the same growth rate. Obviously, power technology has become a bottleneck. The large current in the circuit will reduce the life and reliability of the product. It can also cause failure when the dynamic voltage drop of the power supply is severe.

Where does power consumption come from?

Power consumption is generally divided into two types: dynamic power consumption from switches, and static power consumption from leakage. The dynamic power consumption can be divided into capacitor charging and discharging (including network capacitance and input load), and the instantaneous short-circuit current formed when the P / N MOS is turned on at the same time. Static power consumption can also be divided into several categories: the reverse bias current (Idiode) of the diode formed by the diffusion region and the substrate, and the other type is the current that turns off the gate oxygen through the transistor (Isubthreshold). The leakage of the chip will change with temperature, so when the chip heats up, the static power consumption index rises. In addition, the leakage current will increase as the feature size decreases.

Formula: Ptotal = Pdynamic + Pshort + Pleakage

Pswitch = A * C * V2 * F

Pshort = A (B / 12) (V-2Vth) 3 * F * T

Pleakage = (Idiode + Isubthreshold) * V

How to reduce power consumption?

First define the requirements for power consumption, and then analyze the different architectures to determine the following requirements: system performance, processor and other IP selection, new modules to be designed, target technology, the number of power domains to be considered, target clock frequencies, clock distribution and structure, I / O requirements, memory requirements, analog features and voltage regulation. You also need to define working modes: such as startup, active, standby, idle, and power down, etc. Of course, these modes are determined by both hardware and software .

The ideal solution is to use different operating voltages in different operating modes, but this will cause too complicated situations. For example, you need to consider the isolation of different voltage regions, switching and voltage recovery, and the daily storage recovery of triggers and memories. Missing, etc. To put it simply, you can divide your design based on high performance / high voltage and low performance / low voltage. Next you can consider the system clock structure, which is useful for reducing dynamic power consumption. You can use multiple clock domains, lower the frequency, adjust the phase, and more. The software interface control of general processors can achieve these points. Don't forget the possible problems such as glitch, skew, etc.

Once the architecture is determined, RTL code can be made, of course, the goal is still low power consumption. When using EDA tools, please pay attention to mutiple threshold leakage optimization, multiple supply voltage domains, local latch based clock gating, de-clone and re-clone restructuring, operand isolation, and gate level power optimization.

Let's look at them one by one:

First, mutiple threshold leakage optimization. There are generally three versions of library files: low Vth (fast, large leakage), standard Vth, high Vth (slow, low leakage). Tools generally use high Vth cells as much as possible, and due to timing constraints, low Vth cells are required. Obviously, selecting a library is very important.

Second, multiple voltage domains. Different operating voltages need the support of the library. The division of different voltage regions requires the cooperation of front-end and back-end design.

Third, local latch based clock gating. This is to add a specific clock gating latch before the group of flops.

Fourth, de-clone and re-clone restructuring. Before layout, the local clock gating was raised to a higher level to help reduce area and establish a "clean" starting point for CTS. During specific layout, re-clone the local clock gating to help optimize the clock tree.

Fifth, operand isolation. This step uses a common control signal to automatically identify and close the data path elements and hierarchical combination modules.

Sixth, Classical gate level optimization. Change unit size, pin swapping, remove unnecessary buffers, merge gates, add buffers to reduce skew, adjust logic, etc.

Power consumption analysis of SOC

Most large-scale integrated circuits use CMOS circuits. For CMOS circuits, during a certain task, the energy consumption of one clock cycle is:

In the formula: M is the number of gate circuits in the system, Cm is the load capacitance of the m-th gate circuit, is the number of switching times of each clock cycle of the k-th gate circuit, and Vdd is the power supply voltage of the circuit.

It can be seen that the main factors affecting the power consumption of the system are the operating voltage, load capacitance, the number of switching times of the gate circuit and the number of clocks. These parameters are the starting point for low-power design of SOC systems.

Low-power design at different levels of SOC

The parameter adjustment affecting the power consumption of the system is mainly carried out from the system level to the physical level. The more effective design methods at various levels are described and discussed below.

There are three main methods:

Software and hardware division

The division of software and hardware starts from the abstract description of system functions, and the system functions are decomposed into hardware and software for implementation. By comparing the power consumption of the system functions by hardware and software, a more reasonable low-power implementation scheme is obtained. Because the division of software and hardware is in the initial stage of design, it can bring greater possibilities for reducing power consumption.

Power management

The core idea of power management is to design and distinguish different working modes. Its management methods can be divided into two types: dynamic power management and static power management. The idea of dynamic power management is to selectively suspend modules that are not called, thereby reducing power consumption. Static power management is the management of power consumption in standby mode. What it wants to monitor is the working state of the entire system, not just a certain module. If the system has been idle for a period of time, static power management will suspend the entire chip and the system goes to sleep to reduce power consumption.

Software code optimization

Software code power optimization mainly includes: When determining the algorithm, analyze the complexity and concurrency of the required algorithm, make use of the regularity and reusability of the algorithm as much as possible, and reduce the required computing operations and computing resources. When transforming the algorithm into executable code, optimize it for the specific hardware architecture as much as possible. For example, because accessing registers requires less power than accessing memory, you can reduce access to memory by using registers reasonably and efficiently. Make full use of the power saving mode provided by the hardware in the operating system. With the advent of dynamic voltage scaling technology, the operating system can reduce power consumption by properly setting the operating state.

The main methods of low power design are:

Parallel structure

The parallel structure is completed by dividing the work of one data path into two paths. The main reason for the parallel structure to reduce power consumption is that under the premise that it has the same calculation speed as the reference structure, its operating frequency can be reduced to 1/2, and the power supply voltage can also be reduced. The parallel circuit structure reduces the power consumption by sacrificing the area of the chip. Assume that the operating frequency in the reference structure is., The power supply voltage, and the equivalent capacitance of the entire data path are. In the worst case, the delay is:, then:. If a parallel structure is used, the operating frequency can be reduced to / 2, and the delay in the worst case can reach 2. Assuming that the power supply voltage is reduced to /1.8, the equivalent capacitance is 2 due to the doubling of the circuit and the increase in external wiring. Then: As can be seen from the above formula, the power consumption in the parallel structure has been significantly reduced.

Flowing structure

The circuit pipeline is to reduce the length of the combined path by inserting a register to achieve the purpose of reducing power consumption. The pipeline structure of a pipeline register is inserted in a circuit that is first added and then compared. The adder and selector are on two different combined paths. The operating frequency of the circuit has not changed, but the number of circuits in each stage is reduced, so that the power supply voltage can be reduced. Assuming the power supply voltage is /1.8, the equivalent capacitance becomes 1.2 due to the addition of the pipeline register. Then: As can be seen from the above formula, the use of pipeline structure can also significantly reduce power consumption.

The pipeline and parallelization of the circuit can achieve the purpose of reducing power consumption, because the designer can choose the working voltage of the circuit. If the working voltage of the circuit is fixed, the two methods can only increase the working speed of the circuit, but the power consumption will increase accordingly.

Coding optimization

Generally, One-Hot code, Gray code and bus inversion code can be used to reduce the power consumption of the system bus on chip.

One-Hot code allows only one digit in a binary number to be different from the value of each other digit; Gray code in any two consecutive digits corresponds to only one digit in the binary code. When the content of two adjacent addresses is accessed, the number of transitions is relatively small, thereby effectively reducing the bus power consumption. The bus inversion code considers the relationship between adjacent data when transmitting data to determine the format of the transmission. When the transmitting unit transmits the first data to the bus, it compares it with the first one, and decides whether to send or not according to the result of the comparison, thereby reducing the number of effective flips of the bus, thereby reducing the power consumption of the system.

In addition to these codes, there are some more complex low-power codes, such as narrow bus coding, partial bus inversion coding, and adaptive coding. The ultimate purpose of these coding methods is to reduce the time of switching between different data by changing the coding. The average number of flips. When adopting these codes, the designer should comprehensively consider other costs they bring, such as additional codec circuits. The main methods for low-power design at the register level:

Gated Clock

There are two types of gated clocks: the clock to the logic module and the clock to each flip-flop. But no matter which one, it can play a role in reducing power consumption. The clock control method for the gated logic module is shown in the figure below. The central module provides different gated clocks for module A and module B. When the module is not working, the module can be shut down to achieve the purpose of reducing power consumption.

Module-level clock gating method

The clock control method for gating to each flip-flop is shown below. When the register holds data, the register clock input can be turned off to reduce power consumption.

Gated Clock Control Register

Bucket access

Storage partition access is to divide a large storage module into different small storage modules, and distinguish the different storage modules by the high-order address output by the decoder. During work, only the accessed memory will work, and the other blocks will not work. The architecture of the multi-module RAM is shown below.

Multi-module ram architecture

According to reference [[4], this method can reduce the power consumption of RAM by 12.5%.

Precalculation

Pre-calculation is to perform calculations with smaller bit widths in advance. If the information obtained by these operations can represent the actual operation results, you can avoid performing calculations with larger bit widths and reduce the effective flip rate of the circuit, thereby reducing power consumption the goal of.