What Is a Transceiver Circuit?

Transceiver is a device for signal conversion, usually referred to as a fiber optic transceiver. The emergence of optical fiber transceivers converts twisted pair electrical signals and optical signals to each other, ensuring smooth transmission of data packets between the two networks, and at the same time it extends the transmission distance limit of the network from 100 meters to 100 kilometers (single Mode fiber).

With the continuous development of technology, high-speed serial VO technology has replaced the traditional parallel I / O technology has become the current trend. The fastest parallel bus interface speed is 133 MB / s for ATA7. In 2003, the SATA1.0 specification was released to provide a transfer rate of 150 MB / s, and the SATA3.0. Theoretical speed was 600 MB / s. When the device operates at high speed, the parallel bus is susceptible to interference and crosstalk, which makes the wiring quite complicated. The use of serial transceivers can simplify layout design and reduce the number of connectors. With the same bus bandwidth, the serial interface consumes less power than the parallel port. And the device operating mode changes from parallel transmission to serial transmission, the speed of the serial can be doubled as the frequency increases.

Based on the advantages of the embedded Gb rate level and low power architecture based on FPGA, it enables designers to use high-efficiency EDA tools to quickly solve protocol and rate changes. With the widespread application of FPGAs, transceivers are integrated into FPGAs and become an effective way to solve the problem of device transmission speed ^[1]

Signal integrity

Phase-locked loops (PLL, phase locked loop), CDR (clock and data recovery), 8B / 10B codecs and other mixed-signal module designs in the transceiver have analog signals, such as the voltage-controlled oscillator in the PLL, as well as Digital signals, such as frequency dividers in PLLs. In a chip, there are both analog and digital signals, which easily generate power synchronization noise, ground bounce and signal crosstalk. And the higher data rate of the transceiver means that non-ideal transmission line effects will make wiring more difficult, and the copper wires in each layer will produce a "skin effect". High-frequency signals will sweep across the surface of the conductor, increasing signal attenuation.

2. Jitter

Jitter is the most important parameter for measuring the robustness of a transceiver, because jitter directly reflects the bit error rate of the transceiver. The factors affecting the jitter are the layout of the power and ground, calibration circuits, packaging characteristics, etc., the most important of which is the high-speed clock generated by the PLL. The PLL is very important for clock and data recovery (CDR). The PLL is driven by the input reference clock, so the reference clock input needs to meet strict electrical and jitter requirements.

3. Equalization technology

The data transmitted in the channel inevitably produces inter-symbol interference and various noise effects. In the case of high speed, its interference will be more obvious. In order to overcome transmission interference and loss, an equalizer is inserted in the transceiver system. After equalization correction, the system characteristics can be corrected and compensated, and the influence of inter-symbol interference can be reduced, so that it can adapt to the random change of the channel.

4. Pre-emphasis technology

At Gb-level rates, designers cannot simply address signal loss by amplifying the signal, as this will increase power consumption and cause eye diagrams to close. In the layout, the intensity of the reflected energy shows a near-end discontinuity. Pre-emphasis technology can pre-distortion the transmitted signal by amplifying the first data symbol after any signal change, eliminating the front-end overshoot and trailing-edge tailing of the impulse response in the channel ^[2]

Each high-speed transceiver includes two channels, a transmitter and a receiver. The transmitter and receiver are composed of a physical coding sublayer (PCS, p-field si-cal coding sublayer) and an additional sublayer (PMA, physi-cal). media additional sublayer).

PCS includes hard-core logic implementation compatible with digital functions in transceivers that support the supported protocol. The transmission channel includes modules such as phase compensation FIFO, byte serializer, 8B / 10B encoder; the receiving channel includes word aligner, rate matching FIFO , 8B / 10B decoder, byte deserializer, byte sequencer, phase compensation FIFO and other modules.

PMA includes analog circuits for I / O buffers, CDRs, serializers / deserializers (SER / DES), and programmable pre-emphasis and equalization to optimize serial data channel performance.

When the device transceiver channel is working, the output parallel data in the FPGA architecture is transmitted through the transmitter PCS and PMA, and finally converted into serial data and sent out. The received input serial data is transmitted by the receiver PMA and PCS in the serial data format to the FP to be internal to the architecture for further processing.

High-speed transceivers are widely used. Take the FPGA-based SATA interface solid-state drive as an example. The SATA interface solid-state drive is the development of the future trend. The high-speed serial transceiver implements the SATA IP core storage method. The high-speed transceiver is in the SATA protocol. The key components of the physical layer implementation. SATA protocol serial data works at 1.5-6Gbit / s transmission rate, which cannot be directly implemented by FPGA. In order to meet this demand, many FPGA manufacturers integrate general high-speed physical devices inside the FPGA and provide flexible configuration. Way to accomplish many similar functions.

The high-speed transceiver makes it possible to transmit a large amount of data point-to-point. This serial communication technology makes full use of the channel capacity of the transmission medium. Compared with a parallel data bus, it reduces the number of transmission channels and device pins required, thereby greatly reducing communication. cost. An excellent transceiver should have the advantages of low power consumption, small size, easy configuration, and high efficiency to make it easy to integrate into the bus system. In high-speed serial data transmission protocols, the performance of the transceiver plays a decisive role in the transmission rate of the bus interface, and also affects the performance of this kind of bus interface system to a certain extent. This study analyzes the implementation of the high-speed transceiver module on the FPGA platform, and also provides a useful reference for the implementation of various high-speed serial protocols ^[3] .