What are NAND Hard Drives?

NAND flash memory is a better storage device than hard drives, and it is particularly obvious in low-capacity applications that do not exceed 4GB. As people continue to pursue products with lower power consumption, lighter weight and better performance, NAND has proven extremely attractive. NAND flash memory is a non-volatile storage technology, which can save data even after power off. Its development goal is to reduce the storage cost per bit and increase the storage capacity.

NAND

(Computer Flash Device)

NAND

Each page contains a 2048-byte data area and a 64-byte free area, which contains a total of 2,112 bytes. The free area is usually used for ECC, wear leveling, and other software overhead functions, although it is not physically different from other pages. NAND devices have 8- or 16-bit interfaces. The main data is connected to the NAND memory through an 8- or 16-bit wide bidirectional data bus. In 16-bit mode, instructions and addresses use only the lower 8 bits, while the upper 8 bits are used only during data transfer cycles.

The time required to erase a block is about 2ms. Once the data is loaded into the register, programming a page takes approximately 300 s. Reading a page takes approximately 25 s, which involves accessing the page by the memory array and loading the page into a 16,896-bit register.

Interface consists of 6 main control signals

In addition to the I / O bus, the NAND interface consists of six main control signals:

1. Chip Enable (CE #): If no CE signal is detected, the NAND device will remain in standby mode and will not respond to any control signals.

2. Write Enable (WE #): WE # is responsible for writing data, address or instruction into NAND.

3. Read Enable (RE #): RE # allows output data buffer.

4. Command Latch Enable (CLE): When CLE is high, the instruction is latched into the NAND instruction register on the rising edge of the WE # signal.

5. Address Latch Enable (ALE): When ALE is high, the address is latched into the NAND address register on the rising edge of the WE # signal.

6. Ready / Busy (R / B #): If the NAND device is busy, the R / B # signal will go low. This signal is open-drain and requires a pull-up resistor.

Data is transferred to / from the NAND register each time through a 16-bit or 8-bit interface. When a programming operation is performed, the data to be programmed enters the data register and is on the rising edge of the WE # signal. Random access or movement of data in registers requires special instructions to facilitate random access.

How the data register outputs data

The data register output data is similar to the way using the RE # signal. It is responsible for outputting the existing data and adding it to the next address. The WE # and RE # clocks run extremely fast, reaching a level of 30ns. When RE # or CE # is not low, the output buffer will be tri-stated. This combination of CE # and RE # enables the output buffer, allowing NAND

There are many benefits to choosing a processor or controller with a built-in NAND interface. Without this option, it is possible to design a "glueless" interface between NAND and almost any processor. NAND and NOR

Multi-level cells (MLC) store two bits per cell, while traditional SLC can store only one bit. MLC technology has significant density advantages, however, compared to SLC (Table 3), its speed or reliability is slightly inferior. Therefore, SLC is used in most media cards and wireless applications, while MLC devices are often used in consumer electronics and other low-cost products.

NAND requires ECC to ensure data integrity.

Each page of NAND flash memory includes additional storage space, which is a 64-byte free area (16 bytes per 512-byte sector). This area can store ECC codes and other information such as wear ratings or logical-to-physical block mappings. ECC can be implemented in hardware or software, however, hardware execution has significant performance advantages. During a programming operation, the ECC unit calculates an error correction code based on the data stored in the sector. The ECC code of the data area is then written into the respective free area. When the data is read out, the ECC code is also read out; using the reverse operation can check whether the read out data is correct.

It is possible to use ECC algorithms to correct data errors.

The number of errors that can be corrected depends on the correction strength of the algorithm used. Including ECC in hardware or software provides a powerful system-level solution. The simplest hardware implementation is to use a simple Hamming code, but it can only correct single-bit errors.

Unlike magnetic HDDs, NAND must be in a state where data can be written, without the "write-in-place" function of HDDs. If the data has been written on the NAND, the data must be erased to accept new data. Erasing is a process that breaks thin layers of material.

The simple explanation of the NAND mechanism serves to clarify this slightly, although it is still confusing.

NAND memory is essentially composed of two types of structures called pages and blocks. Each page is most commonly 4/2 KB (it can be other sizes, but this is the most common) and represents a read and write unit. Multiple pages make up a 32/128 KB or 128/512 KB block. NAND reads and writes are performed at the page level. Instead, erasure is performed at the block level. ^[2]