What Are Primary Storage Devices?

Main memory, referred to as main memory. It is an important component of computer hardware. Its role is to store instructions and data, and can be directly and randomly accessed by the central processing unit (CPU). Modern computers are designed to improve performance and take into account reasonable costs, often using multi-level storage systems. That is, a cache memory with a small storage capacity and a high access speed, and a main memory with a moderate storage capacity and a moderate access speed are essential. The main memory stores information by address, and the access speed is generally independent of the address. A 32-bit (bit) address can represent a maximum of 4GB of memory address. This is sufficient for most applications, but it is not enough for some applications with very large calculations and very large databases, so that 64-bit structures are required.

Chinese name: Main memory
Foreign name: Mainmemory
importance: A component of computer hardware

Function: Store instructions and data
Currently: 64-bit
Alias: Main memory

Introduction to Main Memory Development

The main memory is generally a semiconductor memory. Compared with the auxiliary memory, it has the characteristics of small capacity, fast reading and writing, and high price. The main memory in the computer is mainly composed of five parts: a memory bank, a control circuit, an address register, a data register, and an address decoding circuit.

Since the 1970s, the main memory has gradually been composed of large-scale integrated circuits. The most commonly used and most economical dynamic random access memory chip (DRAM). In 1995, DRAM chips with an integration level of 64Mb (which can store 4 million Chinese characters) have begun commercial production, and 16MbDRAM chips have become mainstream products in the market. The access speed of DRAM chips is moderate, generally 50 ~ 70ns. There are some improved DRAMs, such as EDO DRAM (that is, DRAM that expands data output), whose performance can be improved by more than 10% than ordinary DRAM, and SDRAM (that is, synchronous DRAM), whose performance can be improved by about 10% compared to EDO DRAM . In 1998, the successor product of SDRAM was SDRAM (also called DDR, double data rate). In the pursuit of speed and reliability, the more expensive static random memory chip (SRAM) is usually used, and its access speed can reach 1 ~ 15ns. Regardless of whether the main memory is composed of DRAM or SRAM chips, the information stored during power failure will be "lost". Therefore, computer designers should consider maintaining this power supply for several milliseconds to save important information in main memory when this happens. The computer can resume normal operation when power is restored. In view of the above, in some applications, the part that stores important and relatively fixed programs and data in main memory is composed of "non-volatile" memory chips (such as EPROM, flash memory chips, etc.); for completely fixed programs, The data area is even made up of a read-only memory (ROM) chip; these parts of the main memory are not afraid of temporary power interruptions and can prevent virus intrusion.

Main memory technical indicators

Indicator Meaning Performance Unit

Storage capacity The total number of storage units that can be accommodated in one memory. Size of storage space, number of bytes.

KINGXCON DDR2-533

The time it takes for the access time to start to complete a memory operation

The minimum time required for the storage cycle to start two consecutive operations is the speed of main memory ns

Memory bandwidth The amount of information accessed by the memory per unit of time. It is an important technical indicator for measuring the data transmission rate. The unit is b s (bits / second) or B S (bytes / second).

The storage unit that stores a machine word is usually called a word storage unit, and the corresponding unit address is called a word address . A unit that stores one byte is called a byte storage unit , and the corresponding address is called a byte address . If the smallest addressable unit in a computer is a word storage unit, the computer is called a word-addressed computer. If the smallest addressable address in the computer

Gold finger of memory with electroplating process Bits are bytes and the computer is called a byte-addressed computer. A machine word can contain several bytes, so a memory location can also contain several byte addresses that can be individually addressed. For example, in a PDP-11 series computer, a 16-bit binary word storage unit can store two bytes, which can be addressed by a word address or by a byte address. When addressing with a byte address, a 16-bit memory location occupies two byte addresses.

Main memory capacity

The total number of storage units accommodated in a memory is often referred to as the storage capacity of the memory. The storage capacity is expressed by the number of words or bytes (B), such as 64K words, 512KB, 10MB. In order to indicate a larger storage capacity in the external storage, MB, GB, TB and other units are used. 1KB = 2 ^ 10B, 1MB = 2 ^ 20B, 1GB = 2 ^ 30B, 1TB = 2 ^ 40B. B represents a byte, and a byte is defined as 8 binary bits, so the word length of a word in a computer is usually a multiple of 8. The concept of storage capacity reflects the amount of storage space.

Main memory time

Also known as memory access time or read / write time, refers to the time elapsed from the start of a memory operation to the completion of the operation. Specifically, the time that elapses from when a read operation command is issued to when the operation is completed and data is read into the data buffer register is the memory access time.

Main memory cycle

Refers to the minimum time required to start two independent memory operations (such as two consecutive read operations) in succession. Generally, the storage period is slightly larger than the storage time, and its time unit is ns

Classification of main memory products

RAM is the main part of the memory. Its content can be read or written according to the address at any time as required. It is stored in the state of some electrical trigger. Information cannot be saved after power failure. And SRAM. RAM generally uses dynamic semiconductor memory devices (DRAM). Because the CPU works faster than the RAM reads and writes, it takes time to wait for the CPU to read and write the RAM, which reduces the CPU's work speed. In order to increase the speed of the CPU to read and write programs and data, a cache component is added between the RAM and the CPU. The content of the cache is a copy of the contents of some storage units in the random access memory (RAM).

ROM is read-only memory. When it leaves the factory, its contents are written by the manufacturer using mask technology. It can only be read but cannot be rewritten. The information has been solidified in the memory, and is generally used to store the system program BIOS and for microprogram control.

PROM is a programmable ROM that can only be written once (same as ROM), but can be written by the user using special electronic equipment after leaving the factory.

EPROM is an erasable PROM that can be read or written. But before a write operation, it must be irradiated with ultraviolet rays to erase all information, and then write with EPROM programmer, you can write multiple times.

EEPROM is an electrically erasable PROM. Similar to EPROM, it can be read or written. In addition, before the write operation, the previous content does not need to be erased first, and the addressed byte or block can be directly modified.

Flash memory (Flash Memory), its characteristics are between EPROM and EEPROM. Flash memory can also use electrical signals for fast delete operations, much faster than EEPROM. However, byte-level deletion cannot be performed, and its integration is higher than that of EEPROM. ^[1]

Main memory connection control

Main memory capacity expansion

Due to the limited capacity of the memory chip, the main memory is often composed of a certain amount of

model Bit expansion of the chip composition: Bit expansion refers to the expansion of the number of bits (increasing the word length), and the number of words in the chip and the number of words in the memory. The connection method of bit extension is to parallelly connect the address line, chip select line and read-write line of each memory chip, and the data lines of each chip are listed separately. Word extension: Word extension means that only the word count is expanded, and The number of digits does not change. The word expansion connects the chip's address line, data line, and read-write control line in parallel, and the chip select signal is used to distinguish between the chip and the word and expand at the same time: when forming a large-capacity container, it is often necessary to use the word number direction and the number of bit directions Expand on the same time.

Main memory chip select

To realize the access to the memory unit by the CPU, the CPU must first select the memory chip, that is, select the chip; then select the corresponding memory unit from the selected chip according to the address code for data access, which is called word selection. Words in the film

structure map The selection is done by the N low-order address lines sent by the CPU. The address lines are directly connected to the address input ends of all memory chips, and the chip select signals of the memory chips are mostly generated by decoding the high-order addresses.

Line selection method:

The line selection method is to directly use the high-order address lines other than on-chip addressing to directly connect to the chip selection ends of each memory chip. When the address line information is 0, the corresponding memory chip is selected. These chip select address lines can only have one bit valid each time, and do not allow multiple bits to be valid at the same time, so as to ensure that only one chip is selected at a time. The line selection method cannot make full use of the system's memory space and divides the address space into isolated areas, which brings certain difficulties to programming.

Full decoding method:

The full decoding method uses all the upper address lines except for on-chip addressing as the input of the address decoder, and the output of the decoder is used as the chip select signal of each chip, and they are connected to the chip select end of the memory chip. To achieve the choice of memory chips. The advantage of the full decoding method is that the address range of each chip is uniquely determined, and is continuous, which is also easy to expand, and does not generate a memory area with overlapping addresses, but the full decoding method requires higher decoding circuits.

Partial decoding method: The so-called partial decoding method uses a part of the high-order address except on-chip addressing to decode to generate a chip select signal, and the partial decoding method generates an address overlap.

Main memory connection method

Hard connection between main memory and CPU: There are three sets of hard connections between main memory and CPU: address bus (AB), data bus (DB), and control bus (CB). Think of main memory as a black box. The memory address register (MAR) and the memory data register (MDR) are the interface between main memory and the CPU. MAR can receive the instruction address of the program counter (PC) or the address of the operand from the operator to determine the unit to be accessed. MDR is a buffer unit that writes data to or reads data from main memory. MAR and MDR belong to main memory from the functional point of view, but are usually placed in the CPU.

Basic operation of CPU on main memory: When CPU reads and writes on main memory

Simulation First, the CPU gives an address signal on the address bus, then issues the corresponding read and write commands, and exchanges information on the data bus. The basic operations of reading and writing are as follows:

Read: The read operation refers to taking information from the storage unit specified by the address sent by the CPU and sending it to the CPU. The operation process is as follows:

Address > MARABCPU sends the address signal to the address bus

Read command from main memory

WaitForMFC waits for memory work completion signal

M (MAR) > DB > MDR read information to CPU via data bus

Write: The write operation refers to storing the information to be written into the storage unit designated by the CPU. The operation process is:

Address > MAR > ABCPU sends the address signal to the address bus

Data > MDR > DBCPU sends the data to be written to the data bus

Write command from main memory

WaitForMFC waits for memory work completion signal

Speed matching between CPU and main memory: synchronous memory read and asynchronous memory read.

Asynchronous memory read: There is no unified clock between the CPU and main memory, and the main memory work completion signal (MFC) notifies the CPU that the "main memory work has completed".

Synchronous memory read: The CPU and main memory use a unified clock and work synchronously. Because the main memory speed is slow, the CPU must slow down with it. In this type of memory, the main memory work completion signal is not required.

Main memory application technology

Main memory fast read and write

Fast page work technology (fast read and write technology for dynamic memory): When reading and writing data in the same row of dynamic memory, its row address remains locked after the first read and write, and data in multiple columns of the row is read and written in the future At this time, only the column address can be latched, which saves the time of latching the row address and speeds up the reading and writing speed of the main memory.

EDO (ExtendedDataOut) technology: In the fast page work technology, the data latch circuit of the data output part is added to extend the effective holding time of the output data, so that the address signal is changed, and the correct read data can still be obtained, which can be further The address entry time is shortened, and the read and write speed of the main memory is further accelerated.

Main memory read and write in parallel

It refers to the technology used to read multiple main memory words in one work cycle (or longer) of the main memory.

Solution 1: Integrated multi-word structure, that is, increasing the data bits included in each main memory unit to store several main memory words at the same time, then each read operation reads several main memory words simultaneously.

Solution 2: Multi-bank cross-addressing technology, which divides the main memory into several main bodies that can be read and written independently, and the length of each main memory word is read and written separately for each bank; several banks can also be coordinated Runs to provide higher read and write speeds than a single bank.

There are two ways to read and write:

1 Start all main memory reads or writes in the same read and write cycle at the same time.

2 Let the main memory read or write sequentially, that is, each memory word read out in sequence, you can

Main memory Transfer through the data bus in turn, without having to set up a special data buffer register; secondly, the cross-addressing method is used to sequentially allocate several storage words of consecutive addresses in different memory banks, because according to the locality of program operation Characteristics, the probability of reading and writing the main memory word adjacent to the address is greater in a short time.

Main memory data transfer

The so-called group data transmission is that after the address bus transmits an address once, multiple data can be continuously transmitted on the data bus. Originally, two clock cycles were used for each transmission of data: an address is sent first, followed by a data transmission, that is, to transmit N data, 2N bus clock cycles are required, and the group data transmission method uses only N + 1 Bus clock cycles.

To realize the group data transmission mode, not only the CPU must support this operation mode, but the main memory can also provide a sufficiently high data read and write speed, which is often achieved through measures such as the multi-body structure of the main memory and EDO support of dynamic memory.

Main memory dynamic and static

Main memory static

Composition and Design of Internal Memory in Teaching Computer

(1) Storage principle and internal structure of the chip (P207)

(2) The composition and design of the memory in the teaching computer

Address bus: marked as AB15 AB0, which are driven by the address register AR, which only receives the information output by the ALU.

Control bus: The signal of the control bus is given by the decoder 74LS139, the function is to indicate the type of the bus cycle:

(1) Memory write cycle is marked with MMW signal

(2) Memory read cycles are marked with MMR signals

Related illustrations (2 photos)

(3) Peripheral (interface) write cycles are marked with IOW signals

(4) Read cycle of peripheral (interface) is marked with IOR signal

(5) The presence of work is marked with the MMREQ signal

(6) Peripherals are marked with IOREQ signals at work

(7) Write control and storage cycle is marked with SWA signal

Data bus: It is divided into internal data bus IB and external data bus DB. It mainly completes the data transfer between the functional components of the computer. The core technology of designing the bus is to ensure that only one set of data can be sent to the bus at any time, but allow one or more components to receive information on the bus at the same time. The circuit used is usually a tri-state gate.

System clock and timing: teaching machine crystal oscillator is 1.8432MHz. After dividing by 3, the clock of 614.4KHz is used as the system main clock to make the CPU, memory and IO run synchronously. Some registers inside the CPU use a rising edge at the end of the clock to complete receiving data, while general purpose registers are received with a low level. During memory or I / O read and write operations, each bus cycle consists of two clocks. The first clock, called the address time, is used to transfer addresses; the second clock, called the data time, is used to read and write data.

Word expansion of static memory:

The internal memory of the teaching computer is realized by a static memory chip, which is composed of a ROM area of 2K words and a RAM area of 2K words. The memory word is 16 bits long and is word-addressable. ROM consists of 74LS2716 read-only memory ROM (2048 memory cells per chip, each unit is 8-bit binary bits) to complete the word length expansion. The address is allocated in: 0 ~ 2047 RAM, 74LS6116 random memory RAM (2048 memory cells per chip, each unit is 8-bit binary bits), two chips to complete the word length expansion. Addresses are allocated from 2048 to 4095.

Static memory address allocation:

In order to access 2048 memory cells, an 11-bit address is used to send the lower 11 bits of the address bus to the address pins of each memory chip; the upper bits of the address bus are decoded, and the decoded signals are sent to the memory chips. / CS pin for byte-reading in word-addressable memory systems.

Main memory dynamics

Periodic refresh of dynamic memory: When no read or write operation is performed, each unit of the DRAM memory is in a power-off state. Due to the existence of the leakage, the charge stored in the capacitor CS will slowly leak out. Therefore, it must be supplemented regularly. This is called a refresh operation.

(1) the composition of dynamic memory: a single MOS tube to store a bit of binary information. The information is stored in the parasitic capacitance CS of the source of the MOS tube.

When writing data: the word line is high and T is on.

When 1 is written, the bit line (data line) is low and VDD (power) will charge the capacitor

When 0 is written, the bit line (data line) is at a high level. If the capacitor stores electric charge, the capacitor will be discharged completely, indicating that 0 is stored.

When reading data: first make the bit line (data line) high, and T is turned on when the word line is high. If the capacitor originally has a charge ("1"), the capacitor will be discharged. Will cause the data line potential from high to low; if the capacitor has no stored charge ("0"), the data line potential will not change. Detecting the change in potential on the data line can distinguish whether the read data is 1 or 0.

note

The read operation causes the charge stored in the capacitor to be lost, so it is a destructive read. In order to maintain the original memory content, a write operation must be followed immediately after the read operation, which is called the precharge delay.

To provide the address to the storage unit of the dynamic memory, the address is sent first, and then the address is sent. The reason is that the dynamic memory must be refreshed regularly (such as 2ms). The refresh is not processed as a word, but is refreshed one row at a time.

The read signal on the bit line of the dynamic memory is very small, and it must be connected to a sense amplifier, which is usually implemented by a trigger circuit.

The row address and column address latches in the memory chip receive the row and column addresses in sequence.

RAS, CAS, WE, Din, Dout timing relationship

Main memory main memory optimization

There are no shortage of new technologies on the market to improve data storage efficiency. However, most of these new technologies focus on backup and archiving, not primary storage. However, when enterprises begin to reduce primary storage data, it is important for them to understand the necessary requirements for primary storage optimization.

Primary storage, often referred to as Tier 1 storage, is characterized by storing active data--that is, data that is frequently accessed and requires high performance, low latency, and high availability. Main storage is typically used to support mission-critical applications such as databases, email, and transaction processing. Most key applications have random data access patterns and different access requirements, but they all generate large amounts of data that agencies use to run their businesses. As a result, the organization makes many copies of the data, copies the data for distribution, stores the data, and then backs up and archives the data for safekeeping.

The vast majority of data originates from master data. As data ages, they are often migrated to secondary and tertiary storage. As a result, if organizations can reduce their primary data storage footprint, they will be able to take advantage of these saved capacity and costs during the life of the data. In other words, less primary storage footprint means less data replication, inventory, archiving, and backup.

Trying to reduce the primary storage footprint Storage managers can consider two ways to reduce data: real-time compression and data deduplication.

Until recently, data compression has not been widely used in primary storage applications due to performance issues. However, vendors such as Storwize provide solutions that use real-time, random access compression / decompression technology to compress the data footprint by 15: 1. Higher compression rates and real-time performance make compression solutions a viable option for primary storage data reduction.

Data deduplication technology widely used in backup applications is also being applied to primary storage. So far, data deduplication faces a big challenge, that is, data deduplication processing is offline processing. This is because identifying excess data blocks in files that can be as many as millions can take a lot of time and storage processors to do a lot of work, so very active data can be affected. At present, the major vendors introducing data deduplication technologies include NetApp, Data Domain, and OcarinaNetworks.

Main memory main memory deployment

Zero performance impact of main memory

Unlike backup or archive storage, the performance of an active data set is more critical than the storage capacity that can be saved with some form of data reduction technology. Therefore, the data reduction technique chosen must not affect performance. It must be effective and simple; it must be equivalent to "tap a switch and consume less memory".

Active storage reduction solutions deduplicate active storage only when the data that needs to be deduplicated reaches an inactive state. In other words, this means that in fact only deduplication is performed on files that are no longer accessed but still stored in the active storage pool-near the active storage level.

Deduplication avoids performance bottlenecks by suggesting that only light I / O workloads be deduplicated. As a result, storage of key components of the IT infrastructure has not been optimized. The database is at the top of the list of key components. Since they are Tier 1 storage and extremely active components and are almost always excluded from light workloads, deduplication never analyzes them. As a result, the space they occupy in main storage is not optimized.

On the other hand, a real-time compression system compresses all data flowing through the compression system in real time. This leads to an unexpected benefit beyond saving storage capacity: improved storage performance. When all data is compressed, the amount of data submitted by each I / O request effectively increases, hard disk space increases, and each write and read operation becomes more efficient.

The actual result is that the occupied hard disk capacity is reduced, and the overall storage performance is significantly improved.

The second benefit of primary storage deduplication is that all data is reduced, which achieves capacity savings for all data, including the database. Although real-time data compression in the Oracle environment may cause some performance issues, tests to date have shown improved performance.

Another issue is the performance impact on the storage controller itself. People are asking today's storage controllers to do a lot more than just servo hard drives, including managing different protocols, performing replication, and managing snapshots. Adding another function to these functions may exceed the controller's capacity-even if it can handle additional workloads, it adds a process that storage managers must be aware of as a potential I / O bottleneck. Committing the compression to an external dedicated device eliminates a variable from the performance issue without affecting the storage controller a bit.

High availability of main storage

Many data reduction solutions that focus on secondary storage are not highly available. This is because the backup or archive data they must restore immediately is not as critical as in primary storage. However, even in secondary storage, this concept is gradually no longer fashionable, and high availability is added as an option to many secondary storage systems.

However, high availability is not an optional option in primary storage. The ability to read data from a data reduction format (deduplicated or compressed) must exist. In data reduction solutions where deduplication is integrated into the storage array, redundancy is an inevitable consequence of storage arrays that are almost always highly available.

In the aftermarket deduplication system, a component of the solution provides the client with deduplicated data in its original format. This component is called a reader. The reader must also be highly available and seamlessly highly available. Some solutions have the ability to load a reader on a standard server in the event of a failure. Such solutions are often used on near-active or more suitable archived data; they are less suitable for very active data sets.

Most online compression systems are inserted into the system and on the network, placed (logically) between the switch and storage. As a result, they achieve redundancy due to high availability that is almost always designed to be available at the network infrastructure level. Inserting online dedicated equipment along these paths enables seamless failover without the extra effort of IT managers; it leverages what has already been done on the network.

Save space in main memory

Deploying one of these solutions must result in significant capacity savings. It has no value if reduced primary storage usage results in sub-standard user performance.

Primary data does not have the highly redundant storage mode that backup data typically has. This directly affects overall capacity savings. There are also two ways to achieve master data reduction: data deduplication and compression.

Data deduplication looks for redundant data in near-active files, and the level of data reduction that can be achieved will depend on the environment. In environments with a high level of redundancy, data deduplication can bring significant ROI (return on investment), while other environments can only achieve a 10% to 20% reduction.

Compression is effective for all available data, and while it can save more storage capacity for highly redundant data, it also always brings higher savings with more random data patterns common to main storage applications.

In fact, the higher the data mode redundancy, the greater the space savings due to deduplication. The more random the data pattern, the higher the space savings from compression.

Main memory is application independent

The real benefit may come from all data reduction across data types (regardless of the application or how active the data is). Although the actual reduction rate varies depending on the level of deduplication data or the compression rate of the data, all data must be qualified.

When it comes to archiving or backup, application-specific data reduction has clear value, and there is time to customize the reduction process for such data sets. But for active data sets, the specificity of the application will cause a performance bottleneck and will not bring significant benefits of capacity reduction.

Main memory is independent of storage

In a mixed vendor IT infrastructure, the ability to use the same data reduction tools across all platforms will not only further increase the ROI benefits of data reduction, but also simplify deployment and management. Using a different data reduction method for each storage platform will require extensive training and cause confusion at the management level.

Complementary main memory

After completing all the work of optimizing the main storage mentioned above, when it comes to backing up the main storage, it is best to keep the data in an optimized format (compressed or deduplicated). It would be a waste of resources if the data had to be extended to the original format before being backed up.

Expanding the dataset for backup will require:

Decompress data using storage processor or external reader resources;

Expand network resources to transfer data to backup targets;

Allocate additional resources to the backup storage device that holds the backup data.