What is the cache bus?

Sbachovní sbure is a dedicated high -speed bus that a computer processor uses to communicate with the cache memory. Also known as the rear bus, it works at much higher speed than the system bus. The cache bus directly connects the core core to the cache; It runs independent of the processor bus and transmits data through a wider and less limited path. In most modern processors, the cache bus is used to reduce the time required to read or adjust frequently accessible data.

In the 80s, the cache memory was usually placed on the motherboard, not on the processor itself. It was accessible to the cache to the processor bus, as well as conventional system memory. The amount of cache memory was often relatively small and offered only as an optional system performance improvement. The fast cache memory needed a way to interact with the processor without waiting for a much slower system system and input/output operations to complete. In the middle of the 90s.And most of the new processors of dual bus architecture to solve this problem. A high -speed cache bus has been created to access the cache. This bus is not used for nothing else-all other data transfers use a slower processor bus, also known as the front bus. The processor can use both buses simultaneously, leading to much better performance.

the first construction with dual bus often used cache memory located on the motherboard; A large amount of cache on the chip has not yet been cost -effective due to problems with production yield. Later designs often included a mixture of internal and external cache as the yield improved. Modern processors usually use a large amount of internal cache; Many include 8 megabytes (MB) or more, compared to older patterns that often had only 8 kilobytes (KB). In modern designs whereThe whole CACJE on the chip, the cache bus can be relatively short with a very wide data path, 512 bits in some processors. The bus usually runs at the same speed as the processor itself. The final result is that the cache content can be read or adjusted very quickly.

Each multi -core processor core can have its own cache or share one large common cache. In both cases, the cache bus connects each core to the cache memory. When each processor core has its own separate cache, there may be cohesion problems. For example, when one core updates the data in its cache, further copies of this data in other cache will become outdated or "outdated". One way to solve this type of problem is the use of a special type of cache bus, sometimes called an intermediate bus. This bus combines all cache together so each of them can watch what the others are doing - if one updatesSome shared data, others can immediately reflect new content.