What Is a Chip Socket?

The shell for mounting semiconductor integrated circuit chips plays the role of placing, fixing, sealing, protecting the chip and enhancing the electric heating performance, and also serves as a bridge between the chip's internal world and external circuits-the contacts on the chip are connected to the package shell with wires. On the pins, these pins are connected to other devices through wires on the printed board. Therefore, packaging plays an important role for both CPU and other LSI integrated circuits

Chinese name: Chip package
Object: CPU and other LSI integrated circuits
category: Computer circuit

Function: Place, fix, seal, and protect chips
the company: Intel Corporation
Common types: DIP dual in-line

Chip package introduction

Since Intel Corporation designed and manufactured 4-bit microprocessor chips in 1971, over the past 20 years, CPUs have developed from Intel 4004, 80286, 80386, and 80486 to Pentium, P, P, and P4, from 4-bit, 8-bit, 16-bit, 32-bit development to 64-bit; main frequency from MHz to today's GHz; the number of integrated transistors in CPU chips jumped from more than 2000 to more than 10 million; the scale of semiconductor manufacturing technology has been expanded by SSI, MSI, LSI, VLSI Integrated circuits) to ULSI. The number of input / output (I / O) pins of the package has gradually increased from dozens to hundreds, and may even reach 2000. All this is truly a world change.

Commonly used integrated circuits As for the CPU, everyone is already familiar with it, 286, 386, 486, Pentium, PII, Celeron, K6, K6-2, Athlon ... I believe you can list a long list like a few. But when it comes to the packaging of CPUs and other large-scale integrated circuits, not many people know. The so-called package refers to the housing for mounting semiconductor integrated circuit chips. It not only plays the role of placing, fixing, sealing, protecting the chip and enhancing the thermal conductivity, but also serves as a bridge between the chip's internal world and external circuits-the contact on the chip. The wires are connected to the pins of the package shell, and these pins are connected to other devices through the wires on the printed circuit board. Therefore, packaging plays an important role for CPUs and other LSI (Large Scalc Integrat ~ on) integrated circuits. The emergence of new-generation CPUs is often accompanied by the use of new packaging forms. The chip packaging technology has gone through several generations of changes. From DIP, QFP, PGA, BGA, to CSP to MCM, the technical indicators are more advanced than the first generation, including the ratio of chip area to package area is getting closer to 1, applicable. The frequency is getting higher and higher, and the temperature resistance is getting better and better. The number of pins is increased, the pin pitch is reduced, the weight is reduced, the reliability is improved, and the use is more convenient. ^[1]

Common types of chip packages

DIP Chip package DIP dual in-line

DIP (Dual Inline-pin Package) refers to integrated circuit chips packaged in a dual in-line package. Most small and medium-sized integrated circuits (ICs) use this package. The number of pins generally does not exceed 100. The CPU chip in the DIP package has two rows of pins and needs to be inserted into a chip socket with a DIP structure. Of course, it can also be directly inserted on a circuit board with the same number of solder holes and geometrical arrangement for soldering. When inserting or removing a DIP packaged chip from the chip socket, be careful to avoid damaging the pins.

Features:

Suitable for through-hole welding on PCB (printed circuit board), easy to operate.

The ratio between the package area and the chip area is large, so the volume is also large.

The 8088 in Intel series CPUs adopts this packaging form. Cache and early memory chips also use this packaging form.

Chip package component package type

The distance between the pins of a PQFP (Plastic Quad Flat Package) package is small and the pins are very thin. Generally, large-scale or ultra-large-scale integrated circuits use this package, and the number of pins is generally more than 100. Chips packaged in this form must be soldered to the motherboard using SMD (Surface Mount Device Technology). Chips installed with SMD do not need to punch holes in the motherboard. Generally, there are solder joints of corresponding pins on the motherboard surface. Align the pins of the chip with the corresponding solder joints to achieve soldering to the motherboard. Chips soldered in this way are difficult to remove without special tools.

Chips packaged in PFP (Plastic Flat Package) are basically the same as PQFP. The only difference is that PQFP is generally square, while PFP can be either square or rectangular.

Features:

SMD surface mount technology is suitable for mounting wiring on PCB circuit boards.

Suitable for high frequency use. Easy operation and high reliability.

The ratio between chip area and package area is small.

80286, 80386 and some 486 motherboards in Intel series CPUs use this package.

PGA Chip package PGA pin mesh format

The PGA (Pin Grid Array Package) chip package has multiple square matrix pins inside and outside the chip, and each square matrix pin is arranged at a certain distance along the periphery of the chip. Depending on the number of pins, you can make 2-5 turns. During installation, plug the chip into a dedicated PGA socket. In order to make it easier for the CPU to be installed and removed, starting from the 486 chip, a CPU socket named ZIF appeared, which is specially used to meet the requirements of the PGA packaged CPU for installation and removal.

ZIF (Zero Insertion Force Socket) refers to a socket with zero insertion force. Gently lift the wrench on this socket, and the CPU can be easily and easily inserted into the socket. Then press the wrench back to its original position, and use the squeezing force generated by the special structure of the socket itself to firmly contact the pins of the CPU with the socket. There is absolutely no problem of poor contact. When disassembling the CPU chip, simply lift the wrench on the socket to release the pressure and the CPU chip can be easily removed.

Features:

The plug-in operation is more convenient and the reliability is high.

Can adapt to higher frequencies.

Among Intel series CPUs, 80486, Pentium and Pentium Pro all use this package.

BGA Chip package BGA ball grid array

With the development of integrated circuit technology, packaging requirements for integrated circuits have become more stringent. This is because the packaging technology is related to the functionality of the product. When the frequency of the IC exceeds 100MHz, the traditional packaging method may produce the so-called "CrossTalk" phenomenon, and when the number of IC pins is greater than 208 Pins, The packaging method has its difficulties. Therefore, in addition to using PQFP packaging, most high-pin count chips (such as graphics chips and chip sets) are now using BGA (Ball Grid Array Package) packaging technology. BGA has become the best choice for high-density, high-performance, multi-pin packages such as CPUs and south / north bridge chips on motherboards.

BGA packaging technology can be divided into five categories

PBGA (Plastic BGA) substrate: Generally, it is a multilayer board composed of 2-4 layers of organic materials. Among Intel series CPUs, Pentium II, III, and IV processors use this package.

CBGA (CeramicBGA) substrate: ceramic substrate, the electrical connection between the chip and the substrate is usually installed by flip chip (FlipChip, FC). Among Intel series CPUs, Pentium I, II, and Pentium Pro processors have all used this package.

FCBGA (FilpChipBGA) substrate: rigid multilayer substrate.

TBGA (TapeBGA) substrate: The substrate is a strip-shaped soft 1-2 layer PCB circuit board.

CDPBGA (Carity Down PBGA) substrate: refers to the chip area (also known as cavity area) with a square low depression in the center of the package.

Features:

Although the number of I / O pins has increased, the distance between the pins is much larger than the QFP packaging method, which improves the yield.

Although the power consumption of BGA is increased, it is possible to improve the electrothermal performance due to the controlled collapse chip welding.

The signal transmission delay is small, and the adaptive frequency is greatly improved.

Assembly can be used for coplanar welding, which greatly improves reliability.

After more than ten years of development, the BGA packaging method has entered the practical stage. In 1987, Citizen began to develop chips (ie, BGAs) packaged in plastic ball grid arrays. Later, Motorola, Compaq and other companies also joined the ranks of developing BGA. In 1993, Motorola pioneered the application of BGA to mobile phones. In the same year, Compaq applied it to workstations and PCs. Until five or six years ago, Intel started to use BGA in computer CPUs (ie Pentium II, Pentium III, Pentium IV, etc.) and chipsets (such as i850), which played a role in boosting the expansion of BGA application fields. BGA has become an extremely popular IC packaging technology. Its global market size was 1.2 billion pieces in 2000. It is expected that the market demand in 2005 will increase by more than 70% compared with 2000.

CSP Chip package CSP chip size type

With the global demand for personalized and lightweight electronic products, packaging technology has advanced to CSP (Chip Size Package). It reduces the size of the package size of the chip, so that the size of the bare chip can be as large as the package size. That is, the size of the packaged IC side is no more than 1.2 times the chip, and the IC area is only no more than 1.4 times larger than the die.

CSP packages can be divided into four categories

Lead Frame Type (Traditional lead frame form), representative manufacturers include Fujitsu, Hitachi, Rohm, Goldstar (Goldstar) and so on.

Rigid Interposer Type (Rigid Interposer Type), representing manufacturers such as Motorola, Sony, Toshiba, Panasonic and so on.

Flexible Interposer Type (soft interposer type), the most famous of which is the microBGA of Tessera, CTS's sim-BGA also uses the same principle. Other representative manufacturers include General Electric (GE) and NEC.

Wafer Level Package (Wafer Size Package): Different from the traditional single-chip packaging method, WLCSP is to cut the whole wafer into individual chips. It is known as the future mainstream of packaging technology and has been developed by manufacturers. Including FCT, Aptos, Casio, EPIC, Fujitsu, Mitsubishi Electronics and so on.

Features:

Meet the increasing needs of chip I / O pins.

The ratio between chip area and package area is small.

Greatly shorten the delay time.

The CSP package is suitable for ICs with a small number of pins, such as memory modules and portable electronic products. In the future, it will be widely used in emerging products such as information appliances (IA), digital television (DTV), e-books, wireless network WLAN / GigabitEthemet, ADSL / mobile phone chips, Bluetooth, etc.

MCM Chip package MCM multi-chip modular

In order to solve the problem of low integration and insufficient function of a single chip, multiple high-integration, high-performance, high-reliability chips are used in high-density multilayer interconnection substrates to form a variety of electronic module systems. As a result, MCM (Multi Chip Module) multi-chip module system appeared.

Features:

The package delay time is reduced, which makes it easy to achieve high-speed modules.

Reduce the package size and weight of the whole machine / module.

System reliability is greatly improved. ^[2]

Chip package classification method

Chip packaging packaging materials

Plastic, ceramic, glass, metal, etc.

Chip package package form

Ordinary double-row in-line, ordinary single-row in-line, small double-row flat, small four-row flat, round metal, thick thick film circuit, etc.

Chip package package volume

The largest is a thick film circuit, followed by a dual in-line type, a single in-line type, metal package, double-row flat, and four-row flat are the smallest.

Chip package pin pitch

Ordinary standard type plastic package, double-row, single-row in-line type is generally 2.54 ± 0.25 mm, followed by 2mm (more common in single-line in-line type), 1.778 ± 0.25mm (more common in shrink-type double-in-line type), 1.5 ± 0.25mm, or 1.27 ± 0.25mm (more common in single-row with heat sink or single-row V type), 1.27 ± 0.25mm (more common in double-row flat package), 1 ± 0.15mm (more common in double-row or four-row flat package) , 0.8 ± 0.05 0.15mm (more common in four-row flat package), 0.65 ± 0.03mm (more common in four-row flat package).

Chip package pin width

There are several types of double in-line sealing and rotating, such as 7.4 7.62mm, 10.16mm, 12.7mm and 15.24mm.

Double-row flat packages (including lead length) are generally 6 to 6.5 ± mm, 7.6 mm, 10.5 to 10.65 mm, and so on.

Four-column flat package ( length x width over 40 pins) generally has 10 × 10mm (excluding lead length), 13.6 × 13.6 ± 0.4mm (including lead length), 20.6 × 20.6 ± 0.4mm (including lead length), 8.45 × 8.45 ± 0.5mm (excluding lead length), 14 × 14 ± 0.15mm (excluding lead length), etc. ^[1]

Chip package packaging steps

The chip on board (COB) process firstly covers the silicon wafer placement point with a thermally conductive epoxy (generally epoxy resin doped with silver particles) on the substrate surface, and then the silicon wafer is directly placed on the substrate surface and heat-treated to silicon. The wafer is firmly fixed to the substrate, and then an electrical connection is directly established between the silicon wafer and the substrate by wire bonding ^[3] .

There are two main forms of bare chip technology: one is COB technology, and the other is FlipChip. Chip-on-board packaging (COB), where semiconductor chips are handed over and mounted on a printed circuit board. The electrical connection between the chip and the substrate is achieved by a wire stitching method. The electrical connection between the chip and the substrate is achieved by a wire stitching method, and covered with resin to ensure reliability. . Although COB is the simplest bare chip placement technology, its packaging density is far inferior to TAB and flip-chip bonding technology ^[3] .

COB The main soldering method of chip package COB

(1) Thermal pressure welding

Heat and pressure are used to pressure weld the wire to the weld zone. The principle is that by heating and applying pressure, the weld zone (such as AI) undergoes plastic deformation and simultaneously destroys the oxide layer on the pressure-bonding interface, so that the attraction between the atoms is achieved for the purpose of "bonding". In addition, the two metal interface does not When leveling, heating and pressing, the upper and lower metals can be inlaid with each other. This technology is generally used as a chip COG on a glass plate ^[3] .

(2) Ultrasonic welding

Ultrasonic welding uses the energy generated by an ultrasonic generator to rapidly expand and contract to generate elastic vibration through the transducer under the influence of a magnetic field of ultra-high frequency, which causes the chopper to vibrate accordingly. At the same time, a certain pressure is applied to the chopper. The combination of these two forces drives the AI wire to rapidly rub on the surface of the metallized layer such as (AI film) in the welded area, causing plastic deformation of the AI wire and the surface of the AI film. This deformation also destroys the interface of the AI layer. An oxide layer brings two pure metal surfaces into close contact to achieve interatomic bonding, thereby forming a weld. The main welding material is aluminum wire welding head, which is generally wedge-shaped ^[3] .

(3) Gold wire welding

Ball bonding is the most representative soldering technology in wire bonding, because the current semiconductor package II and triode packages use AU wire ball bonding. In addition, it is easy to operate, flexible, and has strong solder joints (the welding strength of AU wire with a diameter of 25UM is generally 0.07 to 0.09 N / point), and it has no directivity, and the welding speed can be as high as 15 points / second or more. Gold wire welding is also called hot (pressing) (ultra) acoustic welding. The main bonding material is gold (AU) wire. The welding head is spherical and therefore ball welding ^[3] .

COB packaging process

The first step: crystal expansion. The entire LED wafer film provided by the manufacturer is evenly expanded by an expansion machine, so that the LED crystals closely arranged on the surface of the film are pulled apart, and it is easy to spin. Step 2: Adhesive. Place the expanded crystal ring on the surface of the adhesive machine where the silver paste layer has been scraped, and carry the silver paste on the back. Point silver paste. Suitable for bulk LED chips. Use a dispenser to spot the right amount of silver paste on the PCB. The third step: Put the expanded crystal ring with the silver paste into the spine frame, and the operator will puncture the LED chip with a spine pen on the PCB printed circuit board under the microscope. Step 4: Put the spined PCB printed circuit board in a thermal cycle oven and leave it for a period of time. After the silver paste is cured, remove it (not for a long time, otherwise the LED chip coating will bake yellow, that is, oxidize. Cause difficulties). If there is LED chip bonding, the above steps are needed; if there is only IC chip bonding, the above steps are cancelled. Step 5: Stick the chip. Use a dispenser to place an appropriate amount of red glue (or black glue) on the IC position of the PCB printed circuit board, and then use an antistatic device (vacuum suction pen or sub) to place the IC die on the red glue or black glue correctly. Step 6: Dry. Put the glued die into a heat-circulating oven and place it on a large flat heating plate for a period of time, which can also be cured naturally (longer time). Step 7: Bonding (hitting the line). An aluminum wire bonding machine is used to bridge the chip (LED die or IC chip) with the corresponding pad aluminum wire on the PCB, that is, the inner lead of the COB is welded. Step 8: Pre-test. Use special testing tools (there are different equipment for different purposes of COB, the simple is a high-precision regulated power supply) to test the COB board and return the unqualified board for repair. Step 9: Dispensing. A dispensing machine is used to place the adjusted amount of AB glue on the bonded LED die. The IC is encapsulated with black glue, and then the appearance is sealed according to customer requirements. Step 10: Cure. Put the sealed PCB printed circuit board in a thermal cycle oven and leave it at a constant temperature. Different drying times can be set according to requirements. Step 11: Post-test. The packaged PCB printed circuit board is then tested for electrical performance with a special inspection tool to distinguish good from bad ^[3] .

Compared with other packaging technologies, COB technology is cheap (only about 1/3 of the same chip), saves space, and has mature technology. However, any new technology was not perfect when it first appeared. COB technology also has disadvantages such as the need for additional welding and packaging machines, sometimes not keeping up with speed, and the PCB's environmental requirements are more stringent and cannot be maintained. ^[3] .

The layout of some on-board chips (CoB) can improve IC signal performance because they remove most or all of the package, that is, remove most or all of the parasitic devices. However, with these technologies, there may be some performance issues. In all of these designs, the substrate may not connect well to VCC or ground due to the lead frame chip or BGA logo. Possible problems include thermal expansion coefficient (CTE) issues and poor substrate connections ^[3] .

Development of flip chip technology for chip packaging

More than 30 years ago, "flip-chips" came out. At the time, it was titled "C4", or "Controlled Fused Chip Interconnect" technology. The technology first uses copper and then makes high-lead solder balls between the chip and the substrate. The connection between the copper or high-lead solder balls and the substrate is made by fusible solder. Soon afterwards, "flexible materials on caps (FOC)" for the automotive market appeared; others also used Sn caps, that is, evaporative expansion fusible surface or E3 process to further improve the C4 process. Although the C4 process is relatively expensive to implement (including license fees and equipment costs), it still provides many performance and cost advantages for packaging technology. Unlike the wire bonding process, flip-chips can be completed in batches, so it is still more cost-effective ^[3] .

As new packaging technologies and processes continue to emerge at an alarming rate, completing chip designs with thousands of bumps is no longer a major technical obstacle. Small packaging technology engineers can easily complete various electrical, thermal, Mechanical and mathematical simulation. In addition, special tools designed for internal use by some of the world's leading companies are now widely used. To this end, designers can fully use these new tools and new processes to maximize design and minimize time to market ^[3] .

Regardless of people's attitude towards this, flip chip has begun a process and packaging technology revolution, and due to the continuous emergence of new materials and new tools, flip chip technology can continue to change after so many years of development In. In order to meet the ever-changing needs of assembly processes and chip design, new substrate technology is being developed in the field of substrate technology, and simulation and design software is constantly updated. Therefore, how to balance the conflict between the desire to design products with the latest technology and the appropriate style to launch the product becomes a major challenge that must be faced. Due to the changing Internet bandwidth and some other factors listed below, many designers and companies have had to switch to flip chip technology ^[3] .

Other factors include:

Reduce signal inductance-40Gbps (related to the design of the substrate); Reduce power / ground inductance; Improve signal integrity; Best thermal and electrical performance and highest reliability; Reduce package pins Number; Beyond the wire bonding capability, the number of high bumps on the periphery or the entire area array design; Allowed when the pitch is close to 200 m design; S chip shrink (chips limited by solder joints); Allow BOAC design Design of bumps on active circuits ^[3] .