What is a Meta Refresh?

(Computer composition principle concept)

Refresh cycle

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(Computer composition principle concept)

Because the storage bits of DRAM are stored based on the amount of charge in the capacitor, this amount of charge will decrease with time and temperature, so it must be refreshed periodically to maintain the correct information they originally memorized. The time interval at which all the memory cells of the DRAM are restored once is called the refresh cycle.

There are three ways to refresh DRAM: centralized refresh, decentralized refresh, and asynchronous refresh.

Chinese name

Refresh cycle

Foreign name

Refresh Cycle

Subject

Principles of computer composition

related information

Memory, DRAM memory

The time interval at which all the memory cells of the DRAM are restored once is called the refresh cycle.

For example: DRAM refreshes all rows every T ms, then this DRAM refresh cycle is T ms

Because the storage bits of DRAM are stored based on the amount of charge in the capacitor, this amount of charge will decrease with time and temperature, so it must be refreshed periodically to maintain the correct information they originally memorized.

The typical standard is to refresh every 8ms to 16ms, and the refresh cycle of some devices can be greater than 100ms.

(1) Centralized refresh

Refers to refreshing all memory cells in a concentrated period of time within a specified refresh cycle. (Usually the last part of the refresh cycle)

For example: For a 64 * 64 matrix refresh, the access cycle is 0.5us and the refresh cycle is 2ms (accounting for 4,000 access cycles).

The centralized refresh requires a total of 0.5 * 64 = 32us (occupies 64 access cycles). During this time, the memory is only used for refresh, blocking all access operations, and the remaining 3968 access cycles are used to read / write or maintain information.

These 64 access cycles are called "dead time", and the ratio of 64/4000 * 100% = 1.6% is called the dead time rate.

The advantage of this method is high speed, but the disadvantage is long dead time.

(2) Decentralized refresh

Refers to the refreshing of each row of memory cells is completed within each access cycle. Among them, the machine's access cycle is divided into two sections, the first half is used to read / write or maintain information, and the second half is used to refresh.

For example: For a 64 * 64 matrix refresh, the access cycle is 0.5us, and the read and write cycle is 0.5us.

The refresh cycle is: 64 * 1us = 64us. <2ms, it will be added in time before the charge is lost in 2ms.

The advantage is that there is no dead time, and the disadvantage is that it is slow.

(3) Asynchronous refresh

Refers to not specifying a fixed refresh cycle, each row is divided into two points, as long as this row is refreshed within 2ms.

For example: for a 64 * 64 matrix refresh, the access cycle is 0.5us.

To enable each row to be refreshed within 2ms, that is, one row is refreshed every (2ms / 64us), that is, for this row, the interval between the next refresh of it, during which 64 memory refresh cycles will pass before the cycle get it.

The refresh time of each row is still 0.5us, and refreshing a row only stops one access cycle, but for each row, the refresh interval is within 2ms and the dead time is shortened to 0.5us.