What Is a Motherboard Detector?

Computer motherboard fault diagnosis cards are specially produced for diagnosing computer faults.

Computer motherboard troubleshooting card

Computer motherboard troubleshooting card is specially designed for diagnosis

Computer motherboard troubleshooting card indicator function quick checklist

The CLK bus clock should always be on as long as an empty board (no CPU, etc.) is connected to the ISA or PCI, otherwise the CLK signal will be bad.

BIOS Basic I / O Flashes when the motherboard reads the BIOS while it is running.

The IRDY master device only flashes when it is ready for IRDY signal, otherwise it does not light.

The OSC oscillates the main vibration signal of the ISA slot. The power on the empty board should be always on, otherwise the vibration will stop.

In the FRAME frame period, the slot flashes when there is a cyclic frame signal in the PCI slot, and it is always on.

RST resets after turning on or pressing the RESET switch for half a second and turning off must be normal. If it is not off, the reset pin on the motherboard is connected to the acceleration switch or the reset circuit is broken.

The 12V power supply should be on when the board is powered on. Otherwise, there is no such voltage or there is a short circuit on the motherboard.

-12V power supply should be on when the board is empty. Otherwise, there is no such voltage or the main board has a short circuit.

The 5V power supply empty board should be always on when it is powered on, otherwise there is no such voltage or there is a short circuit on the motherboard.

5V power supply should always be on when the board is empty, otherwise there is no such voltage or there is a short circuit on the motherboard. (Only ISA slot has this voltage)

3V3 power supply This is a unique 3.3V voltage of the PCI slot. It should be always on when an empty board is powered on. Some motherboards with a PCI slot do not have this voltage.

Computer motherboard troubleshooting card code comments

C0: Boot detection code shows C0, which is the motherboard BIOS failure or the motherboard chip is broken

C1: C1 was originally used to detect whether the memory passed, it is enough to stop, but the motherboard is also suspected of failure

C3: Memory problems D3, D4: This is a memory problem, but the motherboard memory slots are also possible. Most of them are on AMD boards. At this time, you can take out the CPU fan, tighten the CPU, and then perform a power test

25: 25 is a graphics card or slot problem. Generally, the motherboard can be turned on after clearing the motherboard BIOS. Otherwise, I have changed the graphics card

26 or 2b: Turn on the machine, do not turn on the machine to consider the graphics card

31: Graphics card or slot problem

45: graphics card problem

00: Just go to 00 or FF is the CPU or motherboard chip is broken immediately after booting

FF: directly to 00 or FF is the CPU or motherboard chip is bad immediately after booting, or it may be insufficient power supply (proposed on the 20th floor, thanks)

13: BIOS13 in AMI is normal

75: BIOS failure, just reset BIOS

00: The boot code is displayed at the end as this is normal and has been turned on.

FF: The boot code is displayed at the end as this is normal and has been turned on.

05 If manufacturing tests 1 to 5 are repeated repeatedly, 8042 control status can be obtained. Soft reset / power on determined; ROM is about to start. DMA seems to be working or failing.

06 Make the initial preparation of the chip, disable the video, parity, DMA chip, and clear the DMA chip, all page registers and CMOS shutdown bytes. The ROM has been started to calculate the ROM BIOS check sum and check whether the keyboard buffer is cleared. DMA initial page register read / write test is in progress or failed. 07 Processor test 2 to verify the work of the CPU registers. The ROM BIOS check sum is normal, the keyboard buffer has been cleared, and a BAT (basic guarantee test) command is issued to the keyboard. 08 Initially prepares the CMOS timer, and updates the timer cycle normally. A BAT command has been issued to the keyboard, and a BAT command is about to be written. RAM update check is in progress or failed. 09 EPROM check sum and must be equal to zero to pass. Verify the basic warranty test for the keyboard, and then verify the keyboard command bytes. The first 64K RAM test is in progress. 0A makes the video interface initially ready. The keyboard command byte code is issued, and the command byte data is about to be written. The first 64K RAM chip or data line fails and shifts.

0B Test 8254 channel 0. The keyboard controller command byte is written, and the block / unlock commands for pins 23 and 24 are about to be issued. The first 64K RAM odd / even logic failed. 0C Test 8254 channel 1. Keyboard controller pins 23, 24 have been blocked / unlocked; a NOP command has been issued. The address line of the first 64K RAN failed.

0D 1. Check if the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip matches the initial setting. 3. Video channel test. If it fails, sound the horn. The NOP command has been processed; then the CMOS stop register is tested. Parity failure of the first 64K RAM

0E Test CMOS shutdown byte. CMOS stop register read / write test; CMOS check sum will be calculated. Initialize the input / output port address.

0F Tests extended CMOS. The CMOS checksum has been calculated and the diagnostic bytes are written; CMOS starts initial preparation. .

10 Test DMA channel 0. CMOS has been initially prepared, and the CMOS status register is about to make initial preparations for date and time. The first 64K RAM bit 0 fails.

11 Test DMA channel 1. The CMOS status register has been initially prepared and the DMA and interrupt controller will be disabled soon. The first 64DK RAM bit 1 failure.

12 Test the DMA page register. Disable DMA controller 1 and interrupt controllers 1 and 2; that is, video display and initial preparation of port B. The first 64DK RAM bit 2 fails.

13 Test the 8741 keyboard controller interface. The video display has been disabled and port B has been initially prepared; the chip initialization / memory automatic detection is about to begin. The first 64DK RAM bit 3 fails.

14 Test the memory update trigger circuit. The circuit chip initialization / memory automatic detection ends; the 8254 timer test is about to begin. Bit 4 of the first 64DK RAM failed.

15 Test the first 64K of system memory. The second channel timer is half tested; the 8254 second channel timer is about to complete the test. Bit 5 of the first 64DK RAM failed.

16 Create the interrupt vector table used by 8259. The second channel timer test is over; the 8254 first channel timer is about to complete the test. Bit 6 of the first 64DK RAM failed.

17 Adjust video input / output work, enable if video BIOS is installed. The channel 1 timer test is over; the 8254 channel 0 timer is about to complete the test. The 7th bit of the first 64DK RAM failed.

18 Test the video memory. If the selected video BIOS is passed, it can be bypassed. Channel 0 timer test is over; memory update is about to begin. Bit 8 of the first 64DK RAM failed.

19 Test the interrupt controller (8259) mask bit of channel 1. The memory update has started and the memory update will be completed. The 9th bit of the first 64DK RAM failed.

1A Test the interrupt controller (8259) mask bit of the second channel. Memory update line is being triggered, 15 microsecond on / off time is about to be checked. The 10th bit of the first 64DK RAM failed.

1B Tests the CMOS battery level. The memory update time is 30 microseconds; the basic 64K memory test is about to begin. The 11th bit of the first 64DK RAM failed.

1C test CMOS check sum. The 12th bit of the first 64DK RAM failed.

1D sets the CMOS configuration. The 13th bit of the first 64DK RAM failed.

1E Determines the size of the system memory and compares it to the CMOS value. The 14th bit of the first 64DK RAM failed.

1F test 64K memory up to 640K. The 15th bit of the first 64DK RAM failed.

20 Measure the fixed 8259 interrupt bit. Start a basic 64K memory test; the address line is about to be tested. Slave DMA register test is in progress or has failed.

21 Maintain non-maskable interrupt (NMI) bit (parity or check of input / output channels). Passed address line test; parity is about to be triggered. The main DMA register test is in progress or has failed.

22 Test the interrupt function of the 8259. End of trigger parity; serial data read / write test will begin. The main interrupt mask register test is in progress or has failed.

23 Test protection mode 8086 virtual mode and 8086 page mode. Basic 64K serial data read / write tests are OK; any adjustments before the interrupt vector initialization is about to begin. The slave interrupt mask register test is in progress or has failed.

24 Measure the expansion memory above 1MB. Any adjustments before vector initialization are complete, and the initial preparation of the interrupt vector is about to begin. Set the ES segment address register registry to the upper end of memory.

25 Test all memories except the first 64K. Initial preparation of the interrupt vector is completed; the input / output port of the 8042 will be read out for the rotary intermittent start. Loading interrupt vector is in progress or failed.

26 Test exceptions to protection methods. Read out the input / output port of 8042; the initial preparation of global data is about to start intermittently. Turn on the A20 address line; make it participate in addressing.

27 Determine the cache control or mask RAM. All 1 data initial preparation is complete; any initial preparation after the interrupt vector will then proceed. The keyboard controller test is in progress or has failed.

28 Determine the cache control or special 8042 keyboard controller. Initial preparation after interrupt vector is complete; monochrome mode is about to be set. CMOS power failure / check sum calculation is in progress.

29. The monochrome mode has been set, and the color mode is about to be set. A check of the validity of the CMOS configuration is ongoing.

2A Prepares the keyboard controller for initial preparation. The color mode has been set, and the parity of the trigger just before the ROM test. Empty 64K base memory.

2B Prepares the disk drive and controller initially. Triggers end of parity; any adjustments needed just before controlling the optional video ROM check. Screen memory test is in progress or has failed.

2C Checks the serial port and makes initial preparations. Complete the processing before the video ROM control; you are about to view and control the optional video ROM. Initial screen preparation is in progress or has failed.

2D detects the parallel port and prepares it for the initial. Optional video ROM control has been completed, and control of any other processing after video ROM reply control is about to be performed. The screen retrace test is in progress or has failed.

2E prepares hard disk drives and controllers initially. Restore from processing after video ROM control; if no EGA / VGA is found, perform monitor memory read / write test. Detecting video ROM is in progress.

2F detects the math coprocessor and prepares it for initial preparation. No EGA / VGA found; monitor memory read / write test is about to begin. .

30 Create basic memory and extended memory. Pass display monitor read / write test; scan check is about to be performed. Think the screen works.

31 Detect optional ROM from C800: 0 to EFFF: 0 and make initial preparation. Display memory read / write test or scan check failed, another display memory read / write test is about to be performed. Monochrome monitors work.

32 Program the I / O chips such as COM / LTP / FDD / sound equipment on the motherboard to make them suitable for the setting value. Passes another display memory read / write test; yet another display scan check is performed. A color monitor (40 columns) works.

33. The video monitor inspection is over; the adjustment type of the monitor will be checked using the adjustment switch and the actual card. A color monitor (80 columns) works. 34. The display adapter has been verified; then the display mode will be adjusted. Timer tick interrupt test is in progress or has failed.

35. Finish setting the display mode; the data area of the BIOS ROM will be checked soon. The shutdown test is ongoing or has failed.

36. BIOS ROM data area has been checked; cursors about to set power-on information are about to be set. A-20 failed in the gate circuit.

37. The cursor setting to identify the power-on information has been completed; power-on information will be displayed soon. Unexpected interruption in protection mode.

38. Finish displaying power-on information; new cursor position is about to be read out. RAM test is in progress or address failure> FFFFH.

39. The cursor position has been read and the reference information string will be displayed. .

3A. The end of the citation information string display; the message <ESC> will be displayed soon. Interval timer channel 2 test or failed.

3B Use OPTI chip (only 486) to make auxiliary cache initial preparation. <ESC> found message displayed; virtual mode, memory test is about to begin. A daily clock test is in progress or has failed.

3C Establish flags that allow access to CMOS settings. . Serial port test is in progress or has failed.

3D initialize keyboard / PS2 mouse / PNP device and total memory nodes. . Parallel port test is in progress or has failed.

3E attempts to open the L2 cache. The math coprocessor test is in progress or has failed.

40. Preparations have begun for testing in virtual mode; testing will be coming from video storage. Adjust the CPU speed to exactly match the peripheral clock.

41 The interrupt has been turned on, and the data will be initialized for 0: 0 detection of a memory change (interrupt controller or bad memory). Recovery from video memory verification; descriptor table will be prepared soon. The system board selection failed.

42 The display window enters SETUP. The descriptor table is ready; a virtual test of memory is about to be performed. Extended CMOS RAM failure.

43 If it is a plug and play BIOS, the serial port and parallel port are initialized. Enter virtual mode; interrupt is about to be implemented for diagnostic mode. .

44. Interrupt has been implemented (eg, the diagnostic switch has been turned on; the data will be initially prepared to check that the memory returns at 0: 0.) The BIOS interrupt initializes. 45 Initialize the math coprocessor. The data has been initially prepared; checking the memory rollback at 0: 0 and finding out the size of the system memory. .

46. The test memory has been returned; the memory size has been calculated and a page will be written to test the memory. Check ROM ROM version.

47. The page is about to be written in the extended memory; the basic 640K memory is about to be written to the page. .

48. Basic memory has been written to the page; memory above 1MB is about to be determined. Video inspection, CMOS reconfiguration.

49. Find and check the memory below 1BM; the memory above 1MB will be determined soon. .

4A. Find and check the memory above 1MB; the BIOS ROM data area will be checked soon. Perform video initialization.

4B. The inspection of the BIOS ROM data area is over, it is about to check <ESC> and clear the memory above 1MB for soft reset. .

4C. Clearing the memory above 1MB (soft reset) will clear the memory above 1MB. Shield the video BIOS ROM. .

4D Memory above 1MB has been cleared (soft reset); the size of the memory will be saved. .

4E If an error is detected; an error message is displayed on the display, and wait for the customer to press <F1> to continue. Start memory test: (no soft reset); the first 64K memory test is about to be displayed. Display copyright information.

4F Read and write software and hard disk data, and perform DOS boot. The size of the memory starts to be displayed, and the memory being tested will be updated; serial and random memory tests will be performed. .

50 Store the CMOS value in the current BIOS time zone into the CMOS. Complete memory tests below 1MB; size of high-speed memory for relocation and masking. Send the CPU type and speed to the screen.

51. Test memory above 1MB. .

52 All ISA ROMs are initialized, and finally the PCI is assigned IRQ numbers and other initialization tasks. Memory test above 1MB has been completed; ready to return to real address mode. Enter keyboard detection.

53 If it is not a plug and play BIOS, initialize the serial port, parallel port, and set the values. Save the size of the CPU register and memory, and enter the real address mode. 54. Successfully turned on the real address mode; register to be restored when ready to stop is about to be restored. Scan for "strike keys"

55. The register has been restored and the address line of gate A-20 will be disabled. .

56. The A-20 address line was successfully deactivated; the BIOS ROM data area is about to be checked. The keyboard test ends.

57. BIOS ROM data area checked halfway; proceed. .

58. The check of the data area of BIOS ROM is finished; the message <ESC> will be cleared. Non-setting interrupt test.

59. The <ESC> message has been cleared; the message is displayed; the DMA and interrupt controller tests are about to begin. .

5A.. Display Press F2 to set.

5B... Test the base memory address.

5C ... test 640K base memory.

60 Set the hard disk boot sector virus protection function. Passed DMA page register test; video memory is about to be tested. Test extended memory.

61 Display the system configuration table. Video memory verification is over; testing of DMA # 1 basic registers is about to begin. .

62 Begin system boot with interrupt 19H. Passed the DMA # 1 basic register test; the DMA # 2 register test is about to be performed. Test the extended memory address line. 63. Pass the DMA # 2 basic register test; the BIOS ROM data area is about to be checked. .

64. The BIOS ROM data area is checked halfway and continues. .

65. BIOS ROM data area check is over; DMA devices 1 and 2 will be programmed. .

66. Programming of DMA devices 1 and 2 is complete; initial preparation is to be made using interrupt controller 59. Cache registry for optimized configuration.

67. 8259 Initial preparations have ended; keyboard testing is about to begin. .

68.. Make both external cache and CPU internal cache work.

6A... Test and display the external cache value.

6C... Show blocked content.

6E... Display auxiliary configuration information.

70.. The detected error code is sent to the screen for display.

72.. Check if the configuration is wrong.

74.. Test the real-time clock.

76.. Scan for keyboard errors.

7A ... lock the keyboard.

7C... Set the hardware interrupt vector.

7E... Test whether a math processor is installed.

80. The keyboard test has started and is clearing and checking for stuck keys, which will restore the keyboard. Turn off the programmable input / output device.

81. Find the wrong stuck key of keyboard recovery; test command for keyboard control port is about to be issued. .

82. The keyboard controller interface test is over, that is, the command byte is written and the circular buffer is initially prepared. Detection and installation of fixed RS232 interface (serial port).

83. The command byte has been written and the initial preparation of global data has been completed; it is about to check if there is a key lock. .

84. I have checked for locked keys. I am about to check if the memory is mismatched with CMOS. Detection and installation of fixed parallel ports.

85. Memory size has been checked; soft errors and passwords or bypass arrangements are about to be displayed. .

86. Password checked; programming just before bypass arrangement. Reopen the programmable I / O device and check for fixed I / O conflicts.

87. Programming before scheduling is completed; programming of CMOS scheduling will be performed. .

88. Reset the clear screen from the CMOS scheduler; subsequent programming will take place soon. Initialize the BIOS data area.

89. After the scheduled programming is completed; the power-on screen message will be displayed. .

8A. Display the first screen information. Initialize the extended BIOS data area.

8B. Message displayed: Main and video BIOS are about to be blocked. .

8C. Successfully shielded the main and video BIOS and will begin programming the options after CMOS. Initialize the floppy drive controller.

8D. Optional programming has been scheduled, then the mouse is checked and initial preparations are made. .

8E. Mouse tested and initial preparation completed; hard and soft disks are about to be reset. .

8F. The floppy disk has been checked. The disk will be initially prepared and then be equipped with a floppy disk. .

90. The floppy disk configuration is over; the presence of a hard disk will be tested. The hard disk controller is initialized.

91. The hard disk presence test is over; the hard disk is then configured. Local bus hard disk controller initialization.

92. The hard disk configuration is complete; the data area of the BIOS ROM is about to be checked. Jump to user path 2.

93. The data area of the BIOS ROM has been checked halfway; proceed. .

94. After the data area of the BIOS ROM is checked, the basic and extended memory sizes are set. Close the A-20 address line.

95. Adjust the memory size in response to mouse and hard disk type 47 support; the display memory will be checked soon. .

96. Restore after checking display memory; initial preparation before C800: 0 optional ROM control. "ES Segment" registry cleared.

97. Any initial preparation before C800: 0 optional ROM control is completed, and then the optional ROM inspection and control is performed. .

98. Control of optional ROM is complete; any processing required after optional ROM response control is about to be performed. Find ROM selection.

99. Any initial preparation required after the optional ROM test ends; the timer's data area or printer base address is about to be established. .

9A. Return operation after setting timer and printer basic address; that is, setting RS-232 basic address. Mask ROM selection.

9B. Return after RS-232 base address; initial preparations for coprocessor testing are about to be performed. .

9C. The initial preparation required before coprocessor testing ends; the coprocessor then makes initial preparations. Establish power management.

9D. The coprocessor is initially prepared, and any initial preparation is about to take place after coprocessor testing. .

9E. After completing the initial preparation of the coprocessor, the extended keyboard, keyboard identifier, and number lock will be checked. Open hardware interrupt.

9F. The extended keyboard has been checked, the identification mark is set, and the digital lock is turned on or off, and a keyboard recognition command will be issued. .

A0. Issue a keyboard recognition command; the keyboard recognition mark is about to be restored. Set the time and date.

A1. The keyboard identification mark is restored; then the cache test is performed. .

A2. The cache test is over; any soft errors are about to be displayed. Check the keyboard lock.

A3. The soft error is displayed; the rate of keyboard strike is about to be adjusted. .

A4. Adjust the strike rate of the keyboard. The waiting state of the memory is about to be set. The keyboard repeats the initialization of the input rate.

A5. The memory wait status is set; the screen will be cleared. .

A6. The screen is cleared; parity and non-maskable interrupts are about to start. .

A7. Non-maskable interrupts and parity are enabled; any initial preparation needed to control the optional ROM at E000: 0 is about to be performed. .

A8. The initial preparation of the control ROM before E000: 0 ends, and then any initial preparation required after E000: 0 will be controlled. Clear the "F2" key prompt. A9. Return from control E000: 0 ROM, any initial preparation required after control E000: 0 optional ROM is about to be performed. .

AA. The initial preparation after E000: 0 controls the optional ROM is over; the system configuration is about to be displayed. Scan the "F2" key stroke.

AC.. Enter settings.

AE.. Clear the self-test flag.

B0... Check for non-critical errors.

B2.. Power-on self-test is complete and ready to boot into the operating system.

B4 .. The buzzer sounds.

B6... Detect password settings (optional).

B8... Clear all descriptions.

BC.. Clear the checksum.

The default value of the BE program enters the control chip and conforms to the modifiable binary default value table. . Clear the screen (optional).

BF test CMOS setup value. Detect viruses and prompt for data backup.

C0 initializes the cache. Try to boot with interrupt 19.

C1 memory self-test. Find the "55" "AA" mark in the boot sector.

C3 first 256K memory test. ...

C5 Copy BIOS from ROM for quick self-test. ...

C6 cache self-test. ...

CA detects the Micronies cache, if it exists, and prepares it for initial preparation. ...

CC shuts down the non-maskable interrupt handler. ...

Unexpected exceptions for EE processors. ...

FF gives control of the INI19 boot loader and the motherboard is OK.