What Is Ferroelectric RAM?

FeRAM (Ferroelectric RAM), abbreviated as FeRAM or FRAM, is similar to SDRAM and is a random access memory technology. But because it uses a layer of ferroelectric material to replace the original dielectric, it also has the function of non-volatile memory. Ferroelectric random access memory is a small work related to computer memory.

FeRAM

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FeRAM (Ferroelectric RAM), abbreviated as FeRAM or FRAM, similar to

Ferroelectric memory is a non-volatile memory that will not lose content when power is off. It has the advantages of high speed, high density, low power consumption, and radiation resistance. The ferroelectric materials currently used in memory are mainly perovskite structure series, including PbZr1-xTixO3, SrBi2Ti2O9 and Bi4-xLaxTi3O12. The storage principle of ferroelectric memory is based on the high dielectric constant and ferroelectric properties of ferroelectric materials. According to the operating mode, it can be divided into destructive readout (DRO) and non-destructive readout (NDRO). The DRO mode uses the capacitive effect of a ferroelectric thin film, replaces the conventional charge storage capacitor with a ferroelectric thin film capacitor, and uses the polarization reversal of the ferroelectric thin film to implement data writing and reading.

Ferroelectric random access memory (FeRAM) is based on the DRO operating mode. After this destructive read, data needs to be rewritten, so FeRAM is accompanied by a large number of erase / rewrite operations in the information reading process. With continuous polarization inversion, reliability issues such as fatigue failure occur in such FeRAMs. At present, all ferroelectric memories on the market use this mode of operation. The NDRO mode memory uses a ferroelectric thin film to replace the gate silicon dioxide layer in the MOSFET. The gate polarization state (± Pr) is used to modulate the source-drain current, which makes it significantly increase or decrease. -The relative magnitude of the leakage current can read the stored information without reversing the polarization state of the gate, so its reading method is non-destructive. The ferroelectric field effect transistor (FFET) based on the NDRO operating mode is an ideal storage method. But so far, this kind of ferroelectric memory is still in the laboratory research stage, and has not yet reached the practical level.

Ramtron was the first to successfully produce FeRAM. The company has just launched the highly integrated FM31 family of devices that integrate the latest FeRAM memory for automotive electronics, consumer electronics, communications, industrial control, instrumentation and

(MRAM) FeRAM magnetic random access memory (MRAM)

In principle, the design of MRAM is very tempting. It controls the direction of rotation of the electrons in the ferromagnet to achieve the purpose of changing the read current, so that it has binary data storage capabilities. In theory, a ferromagnet will never fail, so its write count is unlimited. The magnetoresistive element used in the early stage of MRAM development is called a giant magnetoresistance (GMR) structure. This structure consists of two layers of magnetic material above and below, and a metal layer of a non-magnetic material sandwiched between them. Since the large current required by the GMR element becomes an insurmountable difficulty, it cannot meet the requirements of high-density memories. Another structure different from GMR is the magnetic tunnel junction (MTJ), as shown in Figure 1. The biggest difference between MTJ and GMR elements is that it is the insulating layer rather than the metal layer that separates the two magnetic materials. The MTJ element is a magnetic field that modulates the magnetization directions of the upper and lower magnetic layers to become parallel or anti-parallel to establish two stable states. In the anti-parallel state, the electrons passing through this element will be relatively disturbed, so it reflects higher resistance Value; while in the parallel state, the electrons receive less interference to obtain a relatively low resistance value. The MTJ element changes the different resistance states through the strength of the magnetic field generated by the internal metal wire, and records the "0" and "1" signals.

Figure 1 Schematic diagram of MTJ element structure

The main technical challenge MRAM currently faces is that the magnetoresistance is too weak, and the resistance between the two states is only 30% to 40% different. It is still difficult to recognize this difference during the reading and writing process. However, NVE announced in November 2003 that its engineers have developed the highest spin-tunneling junction resistance (SDT) to date. The company uses unique materials that change the tunneling magnetoresistance between the two stable states by more than 70% at room temperature. NVE has licensed the use of its MRAM intellectual property to several companies that are committed to commercializing MRAM, including Motorola.

MRAM samples from companies such as IBM, Motorola and INFINEON have been released one after another, and commercial products of MRAM are expected to be available in the market from 2004 to 2005. In June 2002, Motorola demonstrated the first 1Mb MRAM chip. It is reported that in October 2003, the company introduced a 4Mb MRAM sample using a 0.18mm process to other companies. TOSHIBA and NEC's joint research team plans to use a 0.25mm magnetic tunnel junction and a 0.18mm process, hoping to achieve mass production of 256Mb MRAM in 2005. INFINEON and IBM also jointly announced in June 2003 that the high-speed 128Kb MRAM they developed was produced using the 0.18mm process. It is currently the smallest MRAM product in the industry and is expected to gradually replace the existing memory from 2005 and obtain widely used.

(OUM) FeRAM Phase Change Memory (OUM)

Stanford Ovshinsky published the first paper on amorphous phase change in 1968, and founded amorphous semiconductors. A year later, he first described the memory based on phase change theory: in the process of changing the material from an amorphous state to a crystal, and then back to an amorphous state, its amorphous and crystalline states exhibit different reflective and resistive properties, so Amorphous and crystalline states are used to store "0" and "1", respectively. Later, this theory was called the Aufsinsky electron effect. Phase change memory is an element based on the Ofsinski effect, so it is named as the Ofsinski electrical effect unified memory (OUM), as shown in Figure 2. Theoretically, the advantages of OUM are that the product is small in size, low in cost, can be directly written (that is, the original data does not need to be erased when writing data), and is simple to manufacture. It can be manufactured by adding 2 to 4 mask steps.

Figure 2 Schematic diagram of OUM storage unit structure

OUM is the next-generation non-volatile, high-capacity storage technology that is respected by the world's number one semiconductor chip maker Intel Corporation. Together with Ovonyx, the inventor of the technology, Intel is working on research and development to improve the technology and manufacturability. Intel released a 0.18mm 4Mb OUM test chip in July 2001. This technology stores data by generating two different impedances, high and low, on a sulfide. At the 2003 VLSI conference, Samsung also reported that it successfully developed a small-capacity OUM using Ge2Sb2Te5 (GST) as a storage medium and a 0.25mm process. The operating voltage was 1.1V, and a 1.8x109 read-write cycle was performed. No fatigue occurred.

However, the read and write speed and frequency of OUM are not as good as FeRAM and MRAM, and how to maintain its driving temperature stably is also a technical problem. In July 2003, Intel's SKLai responsible for the development of non-volatile memory and other technologies also pointed out another problem of OUM: Although the storage unit of OUM is small, it requires a large peripheral circuit area, so the chip area is a headache for OUM problem. At the same time, from the current point of view, the production cost of OUM is much higher than Intel expected, and it has become one of the bottlenecks that hinder its development.