What Is Memory Bandwidth?

From a functional perspective, you can think of memory as a bridge or warehouse between the memory controller (usually located in the Northbridge chip) and the CPU. Obviously, the capacity of the memory determines the size of the "warehouse", and the bandwidth of the memory determines the width of the "bridge". Both are indispensable. This is often referred to as "memory capacity" and "memory speed". In addition to memory capacity and memory speed, the latency period is also the key to its performance. When the CPU needs the data in the memory, it will issue a request executed by the memory controller. The memory controller will then send the request to the memory and report the entire cycle (from the CPU to the memory controller) to the CPU when receiving the data. Memory back to the CPU).

Dual Channel DDR Technology

Dual channel DDR technology is a kind of memory control technology. It is very similar to dual channel RDRAM technology. It is based on the existing DDR memory technology.

For different CPU platforms, the importance of memory bandwidth is not the same, and in terms of collocation with memory latency, memory bandwidth also has a lot of knowledge. Okay, please look at the specific evaluation.

1. Analysis of memory bandwidth of AMD-nForce2 platform

Exactly nForce2

Attentive friends may find that in the advertisements of brand machines, the specifications of memory are often only roughly marked with "DDR 256MB" or "DDR2 356MB".

The CPU architecture is a core part of the entire PC system, and the improvement of the CPU architecture's performance requires more than just the CPU's main frequency. The data bandwidth of the CPU and the system's main memory is critical to the performance of the entire CPU architecture. For the Pentium 4 architecture,

	DDR	DDR 2
Maximum clock frequency (in MHz)	533 (non-standard)	1066 (non-standard)
Data bandwidth (GB / s)	4.26GB / s	8.5GB / s
Chip package	FBGA, etc.	TSOP
Operating Voltage	2.5V	1.8V
Supreme Physical Bank	4	8
Highest Logic Bank	4	8
Data prefetch (bit)	2	4

From the above table, it is clear that the working voltage of DDR2 is nearly 30% lower than DDR, and the power consumption can be reduced by about 50% accordingly. The CSP package such as FBGA is used to reduce the module size and improve signal integrity. It increases the air flow space between modules and thus improves thermal performance and reliability. Taken together, it is easier to reach the highest frequencies. Manufacturers can't wait for JEDEC, which is too slow, to launch its own DDR1066 product. This product has a single bandwidth of 8.5GB / s, which is equivalent to dual-channel DDR 533.

Due to the multiplication of the core frequency and the external frequency, and we use the external frequency as the standard to measure the clock frequency of the memory, the data transmission rate is the same compared with the same frequency DDR 2 memory and DDR memory.

It's just an increase in frequency, at most it's a "DDR. Change", not a "DDR 2". The major improvement of DDR2 is that the data prefetch has been increased from 2bit of DDR to 4bit. The so-called 2bit prefetch can be understood as the amount that the memory core passes data to the external I / O buffer once, which can be transmitted twice by the external I / O. And 4bit prefetching is the amount of data that the memory core passes to the external I / O buffer once, which can be transmitted 4 times by the external I / O.

Memory chip frequency also has two kinds of chip core frequency and external frequency: in the DDR era, these two frequencies are the same; but in the DDR2 era, the core frequency becomes half of the external frequency. Why is this? Because of the 2-bit prefetch of DDR, the data transmitted by the core at one time is available for external I / O buffer transmission twice, and the data is transmitted in DDR mode. The data transmission is triggered by the upper and lower edges of the CLK clock, so the external clock frequency is consistent with the core frequency. The 4bit prefetch is different. The number of core transmissions can be used for external I / O buffer transmission 4 times. It also enables DDR transmission, and the external frequency must be twice the core frequency.

DDR3 vs. DDR2 memory bandwidth comparison

Increasing bandwidth is the core mission of DDR3 memory. This is undoubtedly the most prominent PC mission of DDR3. In short, DDR3 was introduced to further increase memory bandwidth and provide sufficient matching indicators for increasingly higher FSB CPUs. The frequency of DDR2 memory needs to reach extreme frequencies such as 1066MHz, but its yield and cost are not ideal. This player-level product cannot enter the mainstream of the market. If you want to cut into higher frequencies at a lower cost, a new generation of solutions will be introduced, which is DDR3 memory. From a technical point of view, the starting frequency of DDR3 memory is already at 1066MHz. Although the delay parameters cannot compete with DDR2 memory, the memory bandwidth of 1600 / 2000MHz products launched in the future will definitely leave the DDR2 memory significantly. Take DDR3 2000MHz as an example, its bandwidth can reach 16GB / s (dual-channel memory solution can reach the theoretical bandwidth value of 32GB / s), so DDR3 memory will definitely become the only high-bandwidth choice for users in the future. In fact, the key to increasing the effective frequency of DDR3 memory is still the old trick, which is to increase the number of prefetch design bits, which is similar to the frequency increase scheme adopted by DDR2. We know that the DDR2 prefetch design bit is 4Bit, which means that the frequency of the DRAM core is only 1/4 of the interface frequency, so the core operating frequency of DDR2-800 memory is 200MHz, and the prefetch design digits of DDR3 memory Raised to 8Bit, the frequency of its DRAM core has reached 1/8 of the interface frequency. In this way, DRAM memory that also runs at 200MHz core operating frequency can reach the equivalent frequency of 1600MHz. This "double" effect is in DDR3 It is still very effective. If 2006 is the first year of dual-core CPUs, then 2007 can be said to be the year of power consumption for PCs, because 2007nian has too much publicity related to power consumption performance ratio. From an environmental perspective, reducing power consumption has Really contributing, the annual power consumption of PCs worldwide is quite amazing. Even if each PC is reduced by 1W, its power saving is very considerable. At the same time that DDR3 memory reaches high bandwidth, its power consumption can be reduced. Its core operating voltage is reduced from 1.8V of DDR2 to 1.5V. Related data predicts that DDR3 will save 30% of power consumption than current DDR2. Of course, we also generate heat. no need to worry. Make a balance between bandwidth and power consumption. Compared with existing DDR2-800 products, the power consumption ratios of DDR3-800, 1066 and 1333 are 0.72X, 0.83X and 0.95X, respectively. Not only the memory bandwidth is greatly improved, the power consumption performance It is also better than the previous generation ^[3] .

Increasing bandwidth is the core mission of DDR3 memory

1.Number of logical banks

There are 4Bank and 8Bank designs in DDR2 SDRAM, the purpose is to meet the needs of future large-capacity chips. And DDR3 is likely to start from 2Gb capacity, so the initial logical bank is eight, and it is also ready for the future 16 logical banks.

2. Packages

Due to the addition of some features to DDR3, there will be an increase in pins. 8-bit chips are packaged in 78-ball FBGA, 16-bit chips are packaged in 96-ball FBGA, and DDR2 is available in 60/68 / 84-ball FBGA packages. And DDR3 must be green packaged and must not contain any harmful substances.

3. Burst Length (BL, Burst Length)

Because the pre-fetch of DDR3 is 8 bits, the burst transmission period (BL, Burst Length) is also fixed at 8, and for DDR2 and early DDR architecture systems, BL = 4 is also commonly used. Bit Burst Chop (burst) mode, that is, a BL = 4 read operation plus a BL = 4 write operation to synthesize a BL = 8 data burst transmission, which can be controlled by the A12 address line This burst mode. And it should be pointed out that any burst interrupt operation will be prohibited in the DDR3 memory and will not be supported. Instead, it will be more flexible burst transmission control (such as 4bit sequential burst).

4. Addressing Timing

Just as the number of delay cycles increases after DDR2 transitions from DDR, the CL cycle of DDR3 will also be improved compared to DDR2. The CL range of DDR2 is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of the additional delay (AL) has also changed. The range of AL for DDR2 is 0 to 4, while there are three options for AL for DDR3, which are 0, CL-1 and CL-2. In addition, DDR3 also adds a new timing parameter-Write Delay (CWD), which will be determined according to the specific operating frequency ^[4] .