What Is a Digital Watchdog?

The watch dog timer (WDT, Watch Dog Timer) is an integral part of the microcontroller, it is actually a counter, generally give the watchdog a number, the watchdog starts counting after the program starts running. If the program runs normally, after some time the CPU should issue an instruction to reset the watchdog to zero and restart counting. If the watchdog is increased to the set value, it is considered that the program is not working properly, forcing the entire system to reset.

Watchdog timer

figure 1

The watchdog timer is a timer circuit.It usually has an input called kicking the dog or service the dog, and an output to the RST end of the MCU. When the MCU is working normally, every other period Time to output a signal to the dog feeding terminal and clear the WDT. If the dog is not fed for more than the specified time (usually when the program is flying), the WDT timer will be exceeded and a reset signal will be given to the MCU to reset the MCU. Prevent the MCU from crashing. The function of the watchdog is to prevent the program from looping, or the program is flying. In consideration of real-time monitoring of the operation status of the single chip microcomputer, a special chip for monitoring the operation status of the single chip computer program, commonly known as "watchdog" integrated circuit (MAX * 9), has been developed. Provides a response to the input pulse flow loss latch fault indication. This circuit can monitor the fan (calculation of the fan's speed output), an oscillating circuit, or a microprocessor software to execute.

A simple circuit (Figure 1) provides a responsive input pulse flow loss latch fault indication. Based on the P-supervisor / watchdog integrated circuit (MAX * 9), this circuit is used to monitor the fan (calculated at the fan's rotational speed output), an oscillating circuit, or a suitable microprocessor software implementation.

During power-up, the active-low reset remains low until the VCC stabilization and reset timeouts expire. Capacitor C passes R until the gate voltage of the FET reaches the threshold (voltage VTH), which turns on the field effect transistor and enables the latching capability. To prevent false triggering, you should set the RC delay time far beyond the reset timeout.

The WDI input (pin 6) must be set to a minimum rate by the switching capacitor CSWT. If this does not happen, the active-low reset goes low, the LED indicator, the connection and pull-low reset, thus locking the low-level reset. The circuit remains active until you cycle VCC or push the switch in this condition. Either turn the FET off and allow the reset to go high.

In order to monitor the fan open-drain speed measurement signal, a 10k pull-up resistor is connected to VCC (pin 8) from the world development indicator. Since the fan needs some time to spin up, the watchdog circuit needs to be disabled for a short delay interval. You can reset this delay capacitor (C2) from ground. Note that this delay must be less than the RC delay mentioned above, or the active-low reset latch may be too short prematurely.

For a fan monitor, set the maximum speed pulse period for the CSWT value according to the formula 5.07 × 106 × CSWT, where CSWT is within a few seconds. If the speed is below this threshold, the active low resets the output low and latches.