What Is a MOS Transistor?

N-channel MOS transistor is a type of metal-oxide-semiconductor (Metal-Oxide-Semiconductor). The structured transistor is referred to as MOS transistor for short. The integrated circuit formed by the MOS tube is called a MOS integrated circuit, and the complementary MOS integrated circuit formed by the PMOS tube and the NMOS tube is a CMOS-IC.

N-channel MOS transistor

Right!

N-channel MOS transistor is a type of metal-oxide-semiconductor (Metal-Oxide-Semiconductor), the structure of the transistor is referred to as MOS transistor, there are P-type MOS tube and N-type MOS tube. The integrated circuit composed of MOS tubes is called MOS integrated circuit, and the complementary MOS integrated circuit composed of PMOS tube and NMOS tube is CMOS-IC.

Chinese name

N-channel MOS transistor

Foreign name

Metal-Oxide-Semiconductor

Short name

MOS transistor

Classification

industry

A MOS tube composed of a p-type substrate and two high-concentration n-diffusion regions is called an n-channel MOS tube. When the tube is turned on, an n-type conductive channel is formed in two high-concentration n-diffusion intervals. The n-channel enhancement type MOS tube must apply a forward bias on the gate, and only when the gate-source voltage is greater than a threshold voltage, there is an n-channel MOS tube generated by a conductive channel. The n-channel depletion MOS transistor refers to an n-channel MOS transistor with a conductive channel when the gate voltage is not applied (the gate-source voltage is zero).

The NMOS integrated circuit is an N-channel MOS circuit. The input impedance of the NMOS integrated circuit is very high, and it is basically not necessary to sink current. Therefore, when CMOS is connected to the NMOS integrated circuit, it is not necessary to consider the current load. NMOS integrated circuits mostly use a single set of positive power supply, and more than 5V. As long as the CMOS integrated circuit selects the same power source as the NMOS integrated circuit, it can be directly connected to the NMOS integrated circuit. However, when directly connecting from NMOS to CMOS, because the high level of the NMOS output is lower than the input high level of the CMOS integrated circuit, a (potential) pull-up resistor R is required. The value of R is generally selected from 2 to 100K.

On a P-type silicon substrate with a lower doping concentration, two N + regions with a high doping concentration are fabricated, and two electrodes are led out by using metal aluminum as a drain d and a source s, respectively.

Then the semiconductor surface is covered with a thin silicon dioxide (SiO2) insulation layer, and an aluminum electrode is installed on the insulation layer between the drain and the source as the gate g.

An electrode B is also drawn on the substrate, which constitutes an N-channel enhancement type MOS transistor. The source and substrate of a MOS tube are usually connected together (most tubes are connected before leaving the factory).

Its gate is insulated from other electrodes.

Figures (a) and (b) are its schematic diagram and representative symbols, respectively. The direction of the arrow in the representative symbol indicates that P (substrate) points to N (channel). The arrow direction of the P-channel enhancement mode MOS tube is opposite to the above, as shown in FIG.

vGS control of iD and channel

When vGS = 0

It can be seen from FIG. 1 (a) that there are two back-to-back PN junctions between the drain d and the source s of the enhanced MOS transistor. When the gate-source voltage vGS = 0, even if the drain-source voltage vDS is added, and regardless of the polarity of vDS, there is always a PN junction in a reverse biased state. There is no conductive channel between the drain-source. So the drain current iD0 at this time.

When vGS> 0

If vGS> 0, an electric field is generated in the SiO2 insulation layer between the gate and the substrate. The direction of the electric field is perpendicular to the surface of the semiconductor and is directed from the gate to the substrate. This electric field can repel holes and attract electrons.

Rejecting holes: Reject holes in the P-type substrate near the gate, leaving immobilized acceptor ions (negative ions) to form a depletion layer. Attracting electrons: The electrons (lessons) in the P-type substrate are attracted to the surface of the substrate.

Formation of conductive channels

When the value of vGS is small and the ability to attract electrons is not strong, there is still no conductive channel between the drain and source, as shown in Figure 1 (b). As vGS increases, more electrons are attracted to the surface layer of the P substrate. When vGS reaches a certain value, these electrons form an N-type thin layer on the surface of the P substrate near the gate and are connected to two N + regions. The N-type conductive channel is formed between the drain and the source, and its conductivity type is opposite to that of the P substrate, so it is also called an inversion layer, as shown in Figure 1 (c). The larger vGS, the stronger the electric field acting on the semiconductor surface, the more electrons attracted to the surface of the P substrate, the thicker the conductive channel, and the smaller the channel resistance.

The gate-source voltage at the beginning of the channel formation is called the turn-on voltage and is represented by VT.

The N-channel MOS tube discussed above cannot form a conductive channel when vGS <VT, and the tube is in the off state. Only when vGSVT, a channel is formed. This type of MOS tube that must form a conductive channel when vGSVT is called an enhanced MOS tube. After the channel is formed, a drain current is generated by applying a forward voltage vDS between the drain and source. ^[1]