What Is a Superscalar Processor?

A superscalar CPU architecture refers to a type of parallel operation that implements instruction-level parallelism in a processor core. This technology can achieve higher CPU throughput at the same CPU frequency.

Superscalar

The pipeline design goal of the early single-shot structure microprocessor was to achieve an average instruction per cycle, but this goal could not meet the requirements of processor performance growth.In order to improve the performance of the processor, the processor is required to have each A cycle can issue multiple instructions. Similar to a digital signal processor with a very long instruction word (VLIW, Very Long Instruction Word) structure, a processor with a superscalar structure also issues and executes multiple instructions in parallel every clock cycle. The difference is that the processor of VLIW uses static scheduling, while the processor of superscalar structure uses dynamic instruction scheduling, and determines whether to execute instructions in parallel according to the resource and data related conditions during instruction execution. Superscalar structure is a contemporary multi-emission microprocessing Widely used micro-architecture ^[1]

In a superscalar microprocessor, multiple instructions can be issued and executed simultaneously in each cycle, but the high frequency of instructions also means that the frequency of correlation ^[2] is also high; and its structure determines the complexity of the correlation. Therefore, the pros and cons of the relevant detection and resolution strategies will directly affect the performance of the superscalar processor. In order to effectively deal with the correlation, a combination of static and dynamic scheduling techniques is required. Static scheduling can reduce the occurrence of correlation during the compilation process ; Dynamic scheduling can discover more ILPs based on the dynamic information of the processor. Dynamic scheduling simplifies the design of the compiler and reduces the dependence of compiled code on hardware, but at the cost of a large amount of hardware overhead.

In a superscalar processor, the instruction emission strategy refers to the relevant detection methods and related processing measures taken during the instruction emission process to determine the order in which the instructions in the instruction queue are issued. Performance of a scalar processor. Designing an efficient instruction firing strategy is a prerequisite for achieving a high-performance superscalar processor. In a superscalar processor, because the instructions are executed out of order, the conditions for determining the end of instruction execution are more complicated, so the superscalar is designed When processing the processor, some measures should be considered to achieve precise interruption ^[2] .