What is an IP Module?

An ip (intellectual property) kernel module is a pre-designed or even verified integrated circuit, device, or component with a certain function. Available for chip designers to assemble or integrate.

IP core module

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An ip (intellectual property) kernel module is a pre-designed or even verified integrated circuit, device, or component with a certain function. Available for chip designers to assemble or integrate.

Commonly used ip kernel modules include various CPUs (32 / 64-bit cisc / risc structured CPUs or 8 / 16-bit microcontrollers / microcontrollers, such as 8051), 32 / 64-bit dsp (such as 320c30), dram, sram, eeprom, flashmemory, a / d, d / a, mpeg / jpeg, usb, pci, standard interface, network unit, compiler, encoder / decoder and analog device module, etc. The rich ip kernel module library provides basic guarantees for the rapid design of ASICs and monolithic systems and for occupying the market as soon as possible.

The ip kernel module has 3 different forms: soft ip core, firm ip core, and hard ip core. 1. Soft IP core Soft IP core is mainly based on the description of the function of the ip module. It describes the functions of ip at a higher level of abstraction, and has been optimized for behavioral design and functional verification. It is usually submitted to users in the form of hdl documents, which generally include logical descriptions, netlists, and some files that can be used for testing but cannot be physically implemented. Using soft ip, users can synthesize the correct gate-level netlist for subsequent structural design, and use the eda synthesis tool to integrate with other external logic circuits to design the required device. Although soft IP has great flexibility and portability, compared with hard IP, because it does not contain any specific physical information, if the subsequent design is improper, it is likely to cause design failure. In addition, the subsequent layout and routing work will also take a lot of time. 2. Hard IP core Hard IP core is mainly based on the description of the physical structure of the ip module. The form it provides to the user is a circuit physical structure mask layout and a full set of process files, which is a full set of technology that can be used. Its advantages are that it has completed all front-end and back-end designs, and has a fixed circuit layout bureau and specific technology, which can ensure performance and shorten the design time of soc. But because its circuit layout and technology are fixed, it also results in poor flexibility and it is difficult to transplant to different processing technologies. 3 Solid IP core Solid IP core is mainly based on the description of the ip module structure, which can be understood as an IP core between hard IP and soft IP. The solid IP is generally submitted to the user in a hybrid form of the gate-level netlist and the corresponding specific process netlist. So that the user can modify it as needed to make it suitable for some achievable process flow. In recent years, the updating cycle of electronic products has been continuously shortened, but the complexity of system chips has been increasing. In order to alleviate this contradiction, soc design generally uses a design method based on ip modules. Because the ip module is pre-designed and verified, the designer can focus on the entire system without having to consider the correctness and performance of each module. This can reduce the design time of the soc chip and reduce Design and manufacturing costs to improve reliability. IP reuse technology makes the chip design from hardware-centric, gradually to software-centric, from gate-level design, to ip module and ip interface level design.

Theoretically, the appearance of the ip module can reduce the research and development costs, reduce the research and development time, and save costs moderately. However, in practical applications, due to the increased complexity of the chip structure, it may also lead to increased testing costs and reduced production yield. Although the design method based on the ip module can simplify the system design and shorten the design time, as the soc complexity increases and the design cycle further shortens, it also brings many problems for the reuse of the ip module: (1) To The integration of the IP module into the SOC requires the designer to fully understand the functions, interfaces, and electrical characteristics of the complex IP module, such as microprocessors, memory controllers, bus arbiters, and so on. (2) As the complexity of the system increases, it is becoming more and more difficult to obtain a completely consistent timing. Even if the layout of each ip module is predefined, integrating them together will still produce some unforeseen problems, such as noise, which have a great impact on the performance of the system. The standardization of the ip module can solve the above problems to a certain extent. In the past, various chip design companies, IP vendors, and eda companies used their own internal specifications as design standards, but as the center of soc design shifted to the user end, the widespread use of ip modules, and the emergence of more and more eda tools, these Internal standards have been unable to meet the needs of soc design. In order to solve the problem of the interface and communication protocol of the ip module, the main suppliers of SOC have developed their own SOC on-chip bus structure standards, such as ibm's core connect and arm's amba. These bus structures are usually associated with a processor architecture, such as powerpc or arm. The need for a unified approach to public communication principles, public design formats, and design quality measurement and assurance has driven the development of soc standardization. Therefore, there are many soc standardization organizations like vsia in the world. Vsia was established in 1996 and currently has more than 200 members. Its goal is to establish unified goals and technical standards for the system-level chip industry. By establishing open standards, Facilitate the integration of different ip modules.