What Is Integrated Circuit Packaging?

The position of the integrated circuit package in the electronics pyramid is both the spire and the base of the pyramid. It is well-founded to say that it is in both positions at the same time. From the perspective of the density of electronic components (such as transistors), IC represents the tip of electronics. But IC is a starting point again. It is a basic structural unit, which is the foundation of most electronic systems in our lives. Similarly, ICs are not just monolithic chips or basic electronic structures. The types of ICs vary widely (analog circuits, digital circuits, RF circuits, sensors, etc.), so the requirements and requirements for packaging are also different. This article makes a comprehensive review of IC packaging technology, and introduces the various materials and processes used in manufacturing these indispensable packaging structures in a thick line.

The position of the integrated circuit package in the electronics pyramid is both the spire and the base of the pyramid. It is well-founded to say that it is in both positions at the same time. From the perspective of the density of electronic components (such as transistors), IC represents the tip of electronics. But IC is a starting point again. It is a basic structural unit, which is the basis of most electronic systems in our lives. Similarly, ICs are not just monolithic chips or basic electronic structures. The types of ICs vary widely (analog circuits, digital circuits, RF circuits, sensors, etc.), so the requirements and requirements for packaging are also different. This article makes a comprehensive review of IC packaging technology, and introduces the various materials and processes used in manufacturing these indispensable packaging structures in a thick line.
Chinese name
IC package
Foreign name
Integrated circuit package
Development Type
IC design, chip manufacturing and packaging testing
Trend
Year by year

Overview of integrated circuit packaging

The position of the integrated circuit package in the electronics pyramid is both the spire and the base of the pyramid. It is well-founded to say that it is in both positions at the same time. From the perspective of the density of electronic components (such as transistors), IC represents the tip of electronics. But IC is a starting point again. It is a basic structural unit, which is the basis of most electronic systems in our lives. Similarly, ICs are not just monolithic chips or basic electronic structures. The types of ICs vary widely (analog circuits, digital circuits, RF circuits, sensors, etc.), so the requirements and requirements for packaging are also different. This article makes a comprehensive review of IC packaging technology, and introduces the various materials and processes used in manufacturing these indispensable packaging structures in a thick line.
Integrated circuit packaging must also fully adapt to the needs and development of electronic complete machines. Due to the different functions of various types of electronic equipment and instruments, their overall structure and assembly requirements are often different. Therefore, integrated circuit packaging must be diverse to meet the needs of various complete machines.
Integrated circuit packaging is advancing with the development of integrated circuits. With the continuous development of various industries such as aerospace, aviation, machinery, light industry, chemical industry, the whole machine is also changing towards multifunctionality and miniaturization. In this way, the integration degree of integrated circuits is required to be higher and higher, and the functions are more and more complicated. Correspondingly, the density of integrated circuit packages is increasing, the number of leads is increasing, the volume is becoming smaller and smaller, the weight is getting lighter, and the replacement is getting faster and faster. The rationality and scientificity of the package structure will directly affect The quality of integrated circuits. Therefore, for manufacturers and users of integrated circuits, in addition to grasping the performance parameters and identifying lead arrangements of various integrated circuits, they must also have knowledge of the overall dimensions, tolerances, structural characteristics, and packaging materials of various integrated circuit packages. A systematic understanding and understanding. In order to prevent integrated circuit manufacturers from degrading integrated circuit performance due to improper packaging selection, and to enable integrated circuit users to use integrated circuits for collection design and assembly, they should reasonably carry out plane layout and space occupation, so as to ensure proper selection and reasonable application. . [1]

IC packaging role

The integrated circuit package not only plays a role of electrically connecting the bonding points in the integrated circuit chip with the outside, but also provides a stable and reliable working environment for the integrated circuit chip, and plays a role of mechanical or environmental protection for the integrated circuit chip. The chip can perform normal functions and guarantee high stability and reliability. In short, the quality of integrated circuit packaging has a great bearing on the overall performance of the integrated circuit. Therefore, the package should have strong mechanical properties, good electrical properties, heat dissipation properties and chemical stability.
Although the physical structure, application fields, and I / O number of ICs vary greatly, the role and function of IC packaging are not much different, and the purpose of packaging is also quite consistent. As a "protector of the chip", the package plays several roles, which can be summarized to have two fundamental functions:
(1) Protect the chip from physical damage;
(2) Redistribute I / O to obtain pin pitches that are easier to handle in assembly. Packaging has other secondary functions, such as providing a structure that is easier to standardize, providing a heat dissipation path for the chip, preventing the chip from generating soft errors caused by alpha particles, and providing a structure that is more convenient for testing and aging tests. . Packaging can also be used to interconnect multiple ICs. Interconnects can be made directly using standard interconnect technologies such as wire bonding. Or use interconnect paths provided by packaging, such as hybrid packaging technology, multi-chip components (MCM), system-in-package (SiP), and other methods included in the broader system volume miniaturization and interconnect (VSMI) concept Interconnecting paths to interconnect indirectly.
With the continuous development of micro-electro-mechanical system (MEMS) devices and lab-on-chip devices, packaging has played more roles: such as limiting the chip's contact with the outside world, meeting the requirements of differential pressure, and meeting chemistry And the requirements of the atmospheric environment. There is also increasing concern and active involvement in the research of optoelectronic packaging to meet the evolving requirements of this important area. In recent years, people's views on the importance and increasing functions of IC packaging have changed greatly. IC packaging has become an area as important as the IC itself. This is because in many cases, the performance of IC is restricted by IC packaging, so people pay more and more attention to the development of IC packaging technology to meet new challenges.

IC packaging revolution

IC package package form

In the early stage of the development of integrated circuits, the package was mainly formed by increasing the number of external leads on the basis of the metal circular shell of a semiconductor transistor. However, the number of leads of a metal circular shell cannot be increased indefinitely due to the structural limitation, and when such package leads are too many, it is not conducive to the testing and installation of integrated circuits, and flat-type packages have appeared. The flat package is not easy to solder. With the development of wave soldering technology, a double-row package has appeared. Due to the development of military technology and the need for miniaturization of the whole machine, the packaging of integrated circuits has undergone new changes, and chip carrier packages, four-sided lead flat packages, pin grid array packages, and carrier tape automatic welding packages have been successively produced. At the same time, in order to meet the needs of integrated circuit development, power-type packaging, hybrid integrated circuit packaging, and constant temperature packaging, anti-radiation packaging, and optoelectronic packaging that meet certain specific environments and requirements have also appeared. And various types of packages are gradually formed into series, the number of leads from several to thousands, which has fully met the needs of the development of integrated circuits.

IC packaging materials

As mentioned above, one of the functions of the integrated circuit package is to protect the chip and prevent the chip from contacting the outside air. Therefore, different processing methods and different packaging materials must be adopted according to the specific requirements and places of use of different types of integrated circuits to ensure that the airtightness of the packaging structure meets the specified requirements. The early packaging materials for integrated circuits used a mixture of organic resins and waxes to achieve packaging by filling or infusion. Obviously, the reliability was poor. Rubber was also used for sealing, which was eliminated because its heat resistance, oil resistance and electrical properties were not ideal. The most widely used and most reliable hermetic sealing materials are glass-to-metal seals, ceramic-to-metal seals, and low-melt glass-to-ceramic seals. Due to the need for mass production and cost reduction, plastic model packaging has emerged in large numbers. It is completed by heating and pressing thermosetting resin through a mold. Its reliability depends on the characteristics and molding conditions of organic resins and additives, but due to its resistance Poor thermal properties and hygroscopicity, not yet comparable to other sealing materials. It is still a semi-air-tight or non-air-tight sealing material.
With the maturity of chip technology and the rapid increase in chip yield, the cost of rear sealing in the overall integrated circuit cost is also increasing, and the changes and development of packaging technology are changing with each passing day.

Integrated Circuit Packaging Standards

The overall dimensions of China's integrated circuit packages are based on the International Electrotechnical Commission (IEC) No. 191 standard. At the same time, reference is also made to the relevant standards of the United States Electronic Device Joint Engineering Association (JEDEC) and the Semiconductor Equipment and Materials International Organization (SEMI). According to China's integrated circuit technology and production, the existing package dimensions of 13 types of semiconductor integrated circuits and the package dimensions of 14 types of film integrated circuits and hybrid integrated circuits have been included in national standards. With the development of technology and production needs, new content and projects will be gradually added in order to continuously supplement and improve.

Development status of integrated circuit packaging

With the rapid growth of the industrial scale, the pattern of the IC design, chip manufacturing and packaging and testing industries is constantly being optimized. In 2010, the year-on-year growth rate of the domestic IC design industry reached 34.8% with a scale of 36.385 billion yuan; the growth rate of the chip manufacturing industry also reached 31.1% with a scale of 44.712 billion yuan; the growth rate of the packaging and testing industry was relatively slow, a year-on-year increase of 26.3% , With a scale of 62.918 billion yuan.
Overall, the proportion of IC design industry and chip manufacturing industry has been increasing year by year, reaching 25.3% and 31% respectively in 2010; the proportion of packaging and testing industry has decreased accordingly, which was 43.7% in 2010. The proportion remains the largest.
At present, China's integrated circuit industry cluster has initially formed an overall industrial spatial pattern that gathers the three major regions of the Yangtze River Delta, the Bohai Rim, and the Pearl River Delta. In 2010, the sales revenue of the integrated circuit industry in the three major regions accounted for nearly 95% of the country's overall industrial scale. The integrated circuit industry is basically distributed in the provincial capital cities and planned single cities along the coast, and presents the distribution characteristics of "one axis and one zone", that is, the development axis along the river from Shanghai in the east to Chengdu in the west, and the coastal industrial zone from Dalian in the north to Shenzhen in the south. It has formed six key cities in Beijing, Shanghai, Shenzhen, Wuxi, Suzhou and Hangzhou.
At the beginning of last year, the State Council issued the "Notice of the State Council on Printing and Distributing Certain Policies to Further Encourage the Development of the Software Industry and the Integrated Circuit Industry", giving the IC industry many preferential policies in terms of finance, taxation, investment and financing, research and development, import and export, talents, and intellectual property rights. The coverage extends from design and production companies to upstream and downstream companies in the industrial chain of packaging, testing, equipment, and materials, and the industrial development policy environment has further improved. According to the national plan, by 2015, the scale of the domestic integrated circuit industry will double again on the basis of 2010, and sales revenue will exceed 300 billion yuan, meeting 30% of domestic market demand. The chip design ability has been greatly improved, a group of core chips with independent intellectual property rights have been developed, and the packaging and testing industry has entered the international mainstream field. During the "Twelfth Five-Year Plan" period, China's integrated circuit industry will enter a new golden development period.
The domestic integrated circuit industry is better than the global market under the influence of macro policies such as broadband acceleration and home appliances going to the countryside. According to statistics from the China Semiconductor Industry Association, China's IC industry sales in 2012 were 215.85 billion yuan, an increase of 11.6% year-on-year.
The development of China's integrated circuit industry has gradually formed a pattern of integrated development of integrated circuit design, integrated circuit manufacturing, and integrated circuit packaging and testing. In 2012, China s IC design industry accounted for 28.8% of sales, manufacturing sales accounted for 23.2%, and packaging and test industry sales accounted for 48.0%.
The report data shows that the domestic integrated circuit output in 2012 was 82.31 billion, an increase of 14.4% year-on-year. In 2012, the import value of Chinese integrated circuit products was US $ 192.06 billion, an increase of 12.8% year-on-year; in 2012, the export value of Chinese integrated circuit products was US $ 53.43 billion, an increase of 64.1% year-on-year.

Development trend of integrated circuit packaging

Over a long period of time, there has been little change in integrated circuit packaging. Flat and dual-in-line packages with 6 to 64 leads can basically meet the needs of all integrated circuits. For higher power integrated circuits, metal round and diamond packages are commonly used. But with the rapid development of integrated circuits, there are more and more integrated circuits with more than 64 or even hundreds of leads. For example, Japan's 4 billion supercomputers use an ECL. For composite circuits, 462-lead PGA is used. In the past, not only the number of leads could not meet the needs, but also the electrical performance of the device was often affected due to structural limitations. At the same time, machine manufacturing is also working to increase the assembly density of printed circuit boards and reduce the size of the machine to improve the performance of the machine. This has also forced integrated circuits to develop new packaging structures and new packaging materials to adapt to this new situation. Therefore, the development trend of integrated circuit packaging generally has the following aspects:
1. Surface-mount packaging will become the mainstream of integrated circuit packaging. The surface-mounted structure of integrated circuits is developed to meet the needs of the entire system, mainly because of the miniaturization and light weight of electronic equipment, which requires the overall structure of the electronic components to be assembled It is made into a chip type so that it can be flatly attached to a printed circuit board pad pre-printed with solder paste, and it is soldered firmly by a reflow soldering process. This method can not only reduce the size and weight of electronic equipment, but also the lead length of these components is very short, which can improve assembly speed and product performance, and enable flexible and automated assembly.
Surface-mount packages generally refer to chip carrier packages, small-profile dual-row packages, and flat-lead flat packages. The emergence of such packages is undoubtedly a major advancement in integrated circuit packaging technology.
2. Integrated circuit packages will have more leads, smaller size, and higher packaging density
With the advent of ultra-large-scale and ultra-large-scale integrated circuits, integrated circuit chips have become larger and larger, with an area of 7mm × 7mm, and the number of package terminals can be hundreds or more. Power consumption and anti-radiation, this requires that the package must have low stress, high purity, high thermal conductivity and small lead resistance, distributed capacitance and parasitic inductance to meet the requirements of more leads, smaller volume and higher packaging density.
To reduce the package size, increase the number of leads. The only way is to reduce the lead spacing of the package. A 40-line dual-inline package has a surface area that is 20% larger than a 68-line H-type carrier package. The main difference is that the lead pitch changes from 2.54mm to 1.27mm or 1.00cmm. It is not difficult to imagine that if the lead pitch is further changed to 0.80mm, O.65mm or even 0 50mm, the surface area of the package will be greatly reduced. However, in order to reduce the lead pitch, this will inevitably bring a series of new problems. For example, in the precision manufacturing of printed wires, a photo-etching etching process must be used instead of the stamping process of the mechanical mold. Research topics in various aspects such as reduction of insulation resistance between leads and increase of step capacitance.
The area of integrated circuit chips is increasing, and the corresponding packaging area is also generally increasing, which poses new challenges to the problem of heat dissipation. This problem is comprehensive, and it is not only related to the chip power, packaging materials, surface area of the packaging structure and the maximum junction temperature, but also to the ambient temperature and cold cooling method. This must be in the choice of materials and structure design. And cooling means to make new efforts.
3. Plastic packaging is still the main packaging form of integrated autonomy
Plastic molded packaging has the advantages of low cost, simple process, and convenient for automated production. Although it is explicitly stated in the military integrated circuit standard that the packaging structure as a whole must not use any organic polymer materials, but still 85% of the total integrated circuit The above uses plastic packaging.
Compared with other packages, the plastic package has the disadvantages that it is a non-hermetic or semi-hermetic package, so it has poor moisture resistance and is susceptible to ion pollution. At the same time, it has poor thermal stability and cannot shield electromagnetic waves. High-reliability integrated circuits should not use this package. However, in recent years, the molding materials, lead frames and production processes of plastic packaging have been continuously improved and improved, and reliability has also been greatly improved. It is believed that on this basis, the proportion of packaging will continue to increase.
4. Direct adhesive packaging will achieve greater development
After the integrated circuit packaging has undergone a plug-in and surface-mount reform, a new packaging structure, the direct bonding type, has been developed and tested to achieve commercial value and has achieved greater development. According to international It is predicted that the proportion of direct adhesive packaging in integrated circuits will increase from 8% in 1990 to 22% in 2000. This rapid rise illustrates the advantages and potential of direct adhesive packaging.
The so-called direct bonding package is to directly bond the integrated circuit chip to a printed circuit board or a strip of plastic film covered with metal leads, and perform an assembly process such as flip-chip bonding, and then cover it with an organic resin droplet. At present, the typical package structures include chip board package (COB), carrier tape automatic soldering package (TAB), and flip chip package (FLIPCHIP). Among them, COB package and TAB package have been widely used in music, voice, clocks and watches. Direct circuits such as program control and camera shutter.
The most important factor for the rapid development of direct adhesive packaging is that it can be applied to large-scale automated or semi-automated production with multiple leads, small pitches, and low cost, and it simplifies the packaging structure and assembly process. For example, the COB package no longer uses the metal outer leads necessary for the previous package; the TAB package uses flip-chip bonding instead of the inner lead bonding necessary for the assembly process. In this way, on the one hand, the workload of bonding is reduced, and on the other hand, the reliability of the integrated circuit is improved by reducing the number of crimping points of the leads.
In China, COB packaging has been mass-produced, and TAB packaging is still in the development stage. It is believed that in the future integrated circuits, such packaging will occupy a certain position and achieve greater development.
5. Miniaturization of power integrated circuit packages has become possible
The packaging structure of power integrated circuits is affected by the thermal conductivity of the packaging material, causing the package volume to be large and not matching with other integrated circuits. It has become one of the concerns, and the key is how to use new packaging materials.
The packaging materials used in power integrated circuits not only require good thermal conductivity, but also low linear expansion coefficient and good electrical and mechanical properties. With the advancement of science, some new materials have begun to be applied to integrated circuits. For example, a new ceramic material, aluminum nitride (AlN), which has a thermal conductivity close to beryllium oxide (BeO) and a linear expansion coefficient close to silicon (Si), will become The main material of the power integrated circuit packaging structure has greatly reduced the volume and improved the performance of the circuit. It is believed that more new materials will participate in this field in the future, so that the power integrated circuit can further reduce the volume.
In addition, the use of Freon's small refrigeration system for forced cooling of power integrated circuits to reduce the surface ambient temperature to solve the power consumption of the package has been implemented in some large computers. In this way, while changing the external design of the packaging structure, using new packaging materials, and then improving external cooling conditions, the thermal performance of the integrated circuit can be further improved.

IC IC package IC package

1.BGA (ball grid array)
Ball contact display, one of the surface mount packages. On the back side of the printed circuit board, a spherical bump is produced in a display manner to replace the pins. An LSI chip is assembled on the front side of the printed circuit board, and then sealed by molding resin or potting. Also called a bump display carrier (PAC). The pin can exceed 200, which is a package for multi-pin LSI. The package body can also be made smaller than QFP (Four-sided Pin Flat Package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; a 304-pin QFP with a pin center distance of 0.5mm is 40mm square. And BGA does not have to worry about pin deformation problems like QFP. This package was developed by Motorola Corporation in the United States and was first adopted in mobile phones and other devices. It may be popularized in the United States in the future. Initially, the center distance of the pins (bumps) of the BGA was 1.5 mm, and the number of pins was 225. There are also some LSI manufacturers currently developing 500-pin BGAs. The problem with BGA is visual inspection after reflow. It is unclear whether an effective visual inspection method is available. Some people think that due to the large center distance of the welding, the connection can be regarded as stable and can only be handled by functional inspection. Motorola Corporation of the United States refers to the package sealed with molded resin as OMPAC, and the package sealed by the potting method is called GPAC (see OMPAC and GPAC).
2.BQFP (quad flat package with bumper)
Flat four-lead package with cushion. One of the QFP packages, protrusions (buffer pads) are provided at the four corners of the package body to prevent the pins from being deformed during shipping. American semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The center distance of the pins is 0.635mm, and the number of pins ranges from 84 to 196 (see QFP).
3, butt joint PGA (butt joint pin grid array) Another name for surface mount PGA (see surface mount PGA).
4. C (ceramic)
Symbol for ceramic package. For example, CDIP stands for ceramic DIP. It is a mark often used in practice.
5.Cerdip
Glass sealed ceramic dual in-line package for ECL RAM, DSP (Digital Signal Processor) and other circuits. Cerdip with glass window is used for ultraviolet erasing EPROM and microcomputer circuit with EPROM inside. The center distance of the pins is 2.54mm, and the number of pins is from 8 to 42. In Japan, this package is referred to as DIP-G (G means glass seal).
6.Cerquad
One of the surface-mount packages is a sealed ceramic QFP, which is used to package logic LSI circuits such as DSPs. Cerquad with window is used to encapsulate EPROM circuits. The heat dissipation is better than plastic QFP, and it can tolerate power of 1.5 ~ 2W under natural air cooling conditions. But packaging costs are 3 to 5 times higher than plastic QFP. The center distance of the pins has various specifications such as 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm. The number of pins is from 32 to 368.
7.CLCC (ceramic leaded chip carrier)
The ceramic chip carrier with pins is one of the surface-mount packages, and the pins are drawn out from the four sides of the package and are T-shaped. With window for encapsulating UV-erasable EPROM and microcomputer circuit with EPROM. This package is also called QFJ, QFJ-G (see QFJ).
8.COB (chip on board)
On-chip chip packaging is one of the bare chip mounting technologies. The semiconductor chip is handed over and mounted on a printed circuit board. The electrical connection between the chip and the substrate is realized by a wire stitching method. Resin covered to ensure reliability. Although COB is the simplest bare chip placement technology, its packaging density is far inferior to TAB and flip-chip bonding technologies.
9.DFP (dual flat package)
Flat package on both sides. It is another name for SOP (see SOP). This term has been used before, but it is basically no longer used.
10.DIC (dual in-line ceramic package)
Another name for ceramic DIP (including glass seal) (see DIP).
11.DIL (dual in-line)
Another name for DIP (see DIP). European semiconductor manufacturers often use this name.
12.DIP (dual in-line package)
Dual in-line package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its applications include standard logic ICs, memory LSIs, and microcomputer circuits. The center distance of the pins is 2.54mm, and the number of pins is from 6 to 64. Package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow body DIP), respectively. However, in most cases, no distinction is made, and they are simply collectively referred to as DIP. In addition, ceramic DIP sealed with low melting glass is also called cerdip (see cerdip).
13.DSO (dual small out-lint)
Small form factor package on both sides. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.
14.DICP (dual tape carrier package)
Double-sided pin carrier package. One of TCP (Tape Loaded Encapsulation). The pins are made on an insulating tape and lead out from both sides of the package. Due to the use of TAB (Automatic Tape Loading Soldering) technology, the package is very thin. Commonly used in liquid crystal display drive LSIs, but most of them are custom products. In addition, the 0.5mm-thick memory LSI book package is in the development stage. In Japan, DICP is named DTP in accordance with the standards of the EIAJ (Japanese Electronic Machinery Industry) Association.
15.DIP (dual tape carrier package)
Ibid. The Japanese Electronic Machinery Industry Association named DTCP (see DTCP).
16.FP (flat package)
Flat package. One of the surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
17, flip-chip
Flip the chip. As one of the bare chip packaging technologies, metal bumps are prepared in the electrode area of the LSI chip, and then the metal bumps are pressure-bonded to the electrode area on the printed substrate. The footprint of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction occurs at the joint, which affects the reliability of the connection. Therefore, the LSI chip must be reinforced with resin, and a substrate material having substantially the same thermal expansion coefficient is used.
18.FQFP (fine pitch quad flat package)
The center of the small pin is QFP. Usually refers to QFP (see QFP) with a pin-to-center distance of less than 0.65mm. Some conductor manufacturers use this name.
19.CPAC (globe top pad array carrier)
Another name for BGA by Motorola, USA (see BGA).
20.CQFP (quad fiat package with guard ring)
Four-lead flat package with guard ring. One of the plastic QFP, the pins are covered with a resin protective ring to prevent bending deformation. Before assembling the LSI on a printed circuit board, cut off the pins from the guard ring and make them into a seagull wing shape (L shape). This package has been mass-produced by Motorola in the United States. The center distance of the pins is 0.5mm, and the maximum number of pins is about 208.
21.H- (with heat sink)
Indicates a mark with a heat sink. For example, HSOP means SOP with heat sink.
22.pin grid array (surface mount type)
Surface mount PGA. Usually PGA is a plug-in package with a lead length of about 3.4mm. Surface mount PGA has display pins on the bottom surface of the package, and its length is from 1.5mm to 2.0mm. The placement method uses a method of bump welding with a printed circuit board, so it is also called bump welding PGA. Because the center distance of the pins is only 1.27mm, which is half smaller than the plug-in type PGA, the package body can not be made much, and the number of pins is more than that of the plug-in type (250 to 528). . The base material of the package is a multilayer ceramic substrate and a glass epoxy printing base. Packaging using multilayer ceramic substrates has become practical.
23.JLCC (J-leaded chip carrier)
J-shaped chip carrier. Refers to the other names of windowed CLCC and windowed ceramic QFJ (see CLCC and QFJ). The name adopted by some semiconductor manufacturers.
24.LCC (Leadless chip carrier)
Leadless chip carrier. Refers to a surface mount package where the four sides of the ceramic substrate have only electrode contact and no leads. It is a package for high-speed and high-frequency ICs, also known as ceramic QFN or QFN-C (see QFN).
25.LGA (land grid array)
Contact display package. That is, a package with an array of state electrode contacts is made on the bottom surface. Just plug in the socket during assembly. Ceramic LGAs with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance) are available for high-speed logic LSI circuits. Compared with QFP, LGA can accommodate more input and output pins in a smaller package. In addition, since the impedance of the leads is small, it is suitable for high-speed LSIs. However, due to the complicated manufacture and high cost of the socket, it is basically not used much now. Demand is expected to increase in the future.
26.LOC (lead on chip)
On-chip lead package. One of the LSI packaging technologies is a structure in which the front end of the lead frame is above the chip. A bump is made near the center of the chip, and electrical connections are made with lead stitching. Compared with the original structure in which the lead frame is arranged near the side of the chip, the chip accommodated in a package of the same size has a width of about 1 mm.
27.LQFP (low profile quad flat package)
Thin QFP. Refers to the QFP with a package body thickness of 1.4mm, which is the name used by the Japan Electromechanical Industry Association based on the new QFP outline specifications.
28. L-QUAD
Ceramic QFP one. Aluminum nitride for package substrates has a base thermal conductivity that is 7-8 times higher than alumina, and has good heat dissipation. The encapsulated frame is sealed with alumina and the chip is sealed with potting, thereby reducing costs. It is a package developed for logic LSI, which allows W3 power under natural air cooling conditions. 208-pin (0.5mm center distance) and 160-pin (0.65mm center distance) LSI logic packages have been developed, and mass production began in October 1993.
29.MCM (multi-chip module)
Multi-chip components. A package in which a plurality of semiconductor bare chips are assembled on a wiring substrate. According to the substrate material, it can be divided into three categories: MCM-L, MCM-C and MCM-D. MCM-L is a module using a common glass epoxy multilayer printed circuit board. The wiring density is not very high and the cost is low. MCM-C is a component that uses multilayer technology to form multilayer wiring and uses ceramic (alumina or glass ceramic) as the substrate, similar to a thick-film hybrid IC using a multilayer ceramic substrate. There is no significant difference between the two. The wiring density is higher than MCM-L.
MCM-D is a component that uses multilayer technology to form multilayer wiring, and uses ceramic (alumina or aluminum nitride) or Si, Al as the substrate. The cabling plot is the highest of the three components, but the cost is also high.
30.MFP (mini flat package)
Small flat package. Alternative name for plastic SOP or SSOP (see SOP and SSOP). The name adopted by some semiconductor manufacturers.
31.MQFP (metric quad flat package)
A classification of QFP according to JEDEC (United States Electronic Equipment Council) standards. Refers to standard QFP (see QFP) where the center distance of the pins is 0.65mm and the body thickness is 3.8mm to 2.0mm.
32.MQUAD (metal quad)
A QFP package developed by Olin Corporation. The substrate and cover are made of aluminum and sealed with an adhesive. Under natural air cooling conditions, it can tolerate a power of 2.5W 2.8W. Japan Shinko Electric Industrial Co., Ltd. was licensed to start production in 1993.
33.MSP (mini square package)
Another name for QFI (see QFI) is often called MSP in the early stages of development. QFI is a name prescribed by the Japan Electromechanical Industry Association.
34.OPMAC (over molded pad array carrier)
Moulded resin seal bump display carrier. The name Motorola uses for molded resin-sealed BGAs (see BGA).
35 P (plastic)
A mark indicating a plastic package. For example, PDIP means plastic DIP.
36.PAC (pad array carrier)
Bump display carrier, another name for BGA (see BGA).
37.PCLP (printed circuit board leadless package)
Printed circuit board leadless package. The name adopted by Fujitsu of Japan for plastic QFN (plastic LCC) (see QFN). lead
There are two specifications of foot center distance: 0.55mm and 0.4mm, which are in the development stage.
38.PFPF (plastic flat package)
Plastic flat package. Another name for plastic QFP (see QFP). The name adopted by some LSI manufacturers.
39.PGA (pin grid array)
Display pin package. One of the plug-in packages has vertical pins on the bottom surface arranged in a display. The packaging substrate is basically a multilayer ceramic substrate. In the absence of a material name, ceramic PGAs are mostly used for high-speed large-scale logic LSI circuits. higher cost. The center distance of the pins is usually 2.54mm, and the number of pins ranges from 64 to 447. In order to reduce costs, the packaging substrate can be replaced with a glass epoxy printed substrate. There are also plastic PG A with 64 to 256 pins. In addition, there is also a short-lead surface-mount PGA (butt-welded PGA) with a lead center distance of 1.27mm. (See Surface Mount PGA).
40.piggy back
Ballast package. Refers to a ceramic package with a socket. The shape is similar to DIP, QFP, QFN. It is used to evaluate the program confirmation operation when developing a device with a microcomputer. For example, plug the EPROM into a socket for debugging. These packages are basically made-to-order products, which are not widely circulated on the market.
41.PLCC (plastic leaded chip carrier)
Leaded plastic chip carrier. One of the surface mount packages. The pins are led out from the four sides of the package and are T-shaped and made of plastic. Texas Instruments Corporation of the United States first adopted it in 64k-bit DRAM and 256kDRAM, and has now been widely used in logic LSI, DLD (or process logic device) and other circuits. The center distance of the pins is 1.27mm, and the number of pins is from 18 to 84. J-shaped pins are not easily deformed and easier to operate than QFP, but visual inspection after soldering is more difficult. PLCC is similar to LCC (also known as QFN). Previously, the only difference was that the former used plastic and the latter used ceramic. But now there have been J-shaped packages made of ceramic and leadless packages made of plastic (labeled as plastic LCC, PC LP, P-LCC, etc.), which can no longer be distinguished. For this reason, the Japan Electromechanical Industry Association decided in 1988 to refer to packages that lead out J-shaped pins from the four sides as QFJ and packages with electrode bumps on the four sides as QFN (see QFJ and QFN).
42 PLCC (plastic teadless chip carrier) (plastic leaded chip currier)
Sometimes it is another name for plastic QFJ, sometimes it is another name for QFN (plastic LCC) (see QFJ and QFN). section
LSI manufacturers use PLCC to indicate leaded packages and P-LCC to indicate leadless packages to show differences.
43, QFH (quad flat high package)
Four-sided thick-body flat package. A type of plastic QFP. In order to prevent the package body from breaking, the QFP body is made thicker (see QFP). The name adopted by some semiconductor manufacturers.
44.QFI (quad flat I-leaded packgac)
Four-sided I-lead flat package. One of the surface mount packages. The pins are drawn from the four sides of the package and are I-shaped downwards. Also called MSP (see MSP). Place the bumper connection to the printed circuit board. Because the pins have no protruding parts, the mounting footprint is smaller than QFP. Hitachi, Ltd. developed and uses this package for video analog ICs. In addition, Japan's Motorola PLL IC also uses this package. The center distance of the pins is 1.27mm, and the number of pins is from 18 to 68.
45.QFJ (quad flat J-leaded package)
Four-sided J-lead flat package. One of the surface mount packages. The pins are drawn from the four sides of the package and are J-shaped downwards. It is a name prescribed by the Japan Electromechanical Industry Association. The center distance of the pins is 1.27mm.
Materials are plastic and ceramic. Plastic QFJ is mostly called PLCC (see PLCC), which is used for circuits such as microcomputers, door displays, DRAM, ASSP, OTP. The number of pins is from 18 to 84.
Ceramic QFJ is also called CLCC, JLCC (see CLCC). Windowed packages are used for UV-erasable EPROMs and microcomputer chip circuits with EPROMs. The number of pins is from 32 to 84.
46.QFN (quad flat non-leaded package)
Four-sided leadless flat package. One of the surface mount packages. It is now called LCC. QFN is a name prescribed by the Japan Electromechanical Industry Association. There are electrode contacts on the four sides of the package. Because there are no pins, the mounting area is smaller than QFP and the height is lower than QFP. However, when a stress is generated between the printed substrate and the package, the electrode contact cannot be alleviated. Therefore, it is difficult to make as many QFP pins as the electrode contacts, usually from 14 to 100. Materials are ceramic and plastic. When there are LCC marks, they are basically ceramic QFNs. The center distance of electrode contacts is 1.27mm.
Plastic QFN is a low cost package based on a glass epoxy printed substrate. In addition to the center distance of electrode contacts, there are two types of 0.65mm and 0.5mm. This package is also called plastic LCC, PCLC, P-LCC, etc.
47.QFP (quad flat package)
Four-lead flat package. One of the surface-mount packages. The pins are drawn from four sides into a seagull wing (L) shape. There are three types of substrates: ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When materials are not specifically indicated, plastic QFPs are mostly used. Plastic QFP is the most popular multi-pin LSI package. Not only for digital logic LSI circuits such as microprocessors and door displays, but also for analog LSI circuits such as VTR signal processing and acoustic signal processing. There are various specifications of the lead center distance of 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm. The maximum number of pins in the 0.65mm center-to-center specification is 304. In Japan, QFP with a center-to-center distance of less than 0.65mm is called QFP (FP). But now the Japanese electronics and machinery industry has re-evaluated the QFP form factor. There is no difference in the pin center distance, but it is divided into three types: QFP (2.0mm ~ 3.6mm thickness), LQFP (1.4mm thickness) and TQFP (1.0mm thickness) according to the package body thickness.
In addition, some LSI manufacturers specifically refer to QFPs with a pin center distance of 0.5mm as shrink-type QFP or SQFP, VQFP. However, some manufacturers also refer to QFP with 0.65mm and 0.4mm lead centers as SQFP, which makes the name slightly confused. The disadvantage of QFP is that when the center distance of the pins is less than 0.65mm, the pins are easily bent. To prevent pin deformation, several improved QFP variants have appeared. For example, BQFP (see BQFP) with tree finger cushions at the four corners of the package; GQFP (see GQFP) with a resin protection ring covering the front end of the pin; test bumps in the package body, TPQFP (see TPQFP) that can be tested in a special fixture. In terms of logic LSI, many development products and highly reliable products are packaged in multilayer ceramic QFP. Products with a minimum lead center distance of 0.4mm and a maximum number of pins of 348 have also been introduced. In addition, glass-sealed ceramic QFP is also available (see Gerqa d).
48.QFP (FP) (QFP fine pitch)
Small center distance from QFP. The name specified by the Japan Electromechanical Industry Association standards. Refers to QFP (see QFP) with a pin center distance of 0.55mm, 0.4mm, 0.3mm, etc., which is less than 0.65mm.
49.QIC (quad in-line ceramic package)
Another name for ceramic QFP. The name adopted by some semiconductor manufacturers (see QFP, Cerquad).
50.QIP (quad in-line plastic package)
Another name for plastic QFP. The name adopted by some semiconductor manufacturers (see QFP).
51.QTCP (quad tape carrier package)
Four-sided pin carrier package. One of the TCP packages. Pins are formed on the insulation tape and lead out from the four sides of the package. It is a thin package using TAB technology (see TAB, TCP).
52.QTP (quad tape carrier package)
Four-sided pin carrier package. The name used by the Japan Electromechanical Industry Association for the outline specifications established by QTCP in April 1993 (see TCP).
53.QUIL (quad in-line)
Another name for QUIP (see QUIP).
54.QUIP (quad in-line package)
Four-row lead-in package. The pins are drawn from the two sides of the package, and every other stagger is bent down into four columns. The lead center distance is 1.27mm. When inserting the printed circuit board, the insert center distance becomes 2.5mm. Therefore it can be used for standard printed circuit boards. It is a smaller package than the standard DIP. Nippon Electric Co., Ltd. has adopted several packages in microcomputer chips such as desktop computers and home appliances. Materials are ceramic and plastic. Number of pins: 64.
55.SDIP (shrink dual in-line package)
Shrinking DIP. One of the plug-in packages, the shape is the same as DIP, but the lead center distance (1.778mm) is smaller than DIP (2.54 mm),
Hence this title. The number of pins is from 14 to 90. Also called SH-DIP. Materials are ceramic and plastic.
56, SH-DIP (shrink dual in-line package)
Same as SDIP. The name adopted by some semiconductor manufacturers.
57.SIL (single in-line)
Another name for SIP (see SIP). European semiconductor manufacturers mostly use the name SIL.
58, SIMM (single in-line memory module)
Single-rank memory module. Memory assembly with electrodes only near one side of the printed substrate. Usually refers to the component plugged into the socket. Standard SIMMs are available in 30 electrodes with a center distance of 2.54mm and 72 electrodes with a center distance of 1.27mm. SIMMs with 1 Mbit and 4 Mbit DRAM in SOJ packages on one or both sides of the printed circuit board have been widely used in personal computers, workstations, and other devices. At least 30-40% of the DRAM is assembled in the SIMM.
59.SIP (single in-line package)
Single in-line package. The pins are drawn from one side of the package and arranged in a straight line. When mounted on a printed circuit board, the package is in a standing position. The lead center distance is usually 2.54mm, and the number of pins is from 2 to 23, most of which are customized products. The shape of the package varies. Some packages with the same shape as ZIP are called SIP.
60. SK-DIP (skinny dual in-line package)
A type of DIP. Refers to a narrow body DIP with a width of 7.62mm and a lead center distance of 2.54mm. Commonly referred to as DIP (see DIP).
61. SL-DIP (slim dual in-line package)
A type of DIP. Refers to a narrow body DIP with a width of 10.16mm and a lead center distance of 2.54mm. Commonly referred to as DIP.
62.SMD (surface mount devices)
Surface mount devices. Occasionally, some semiconductor manufacturers classify SOPs as SMD (see SOP).
63.SO (small out-line)
Another name for SOP. Many semiconductor manufacturers in the world use this nickname. (See SOP).
64.SOI (small out-line I-leaded package)
Small I-lead package. One of the surface mount packages. The pins are drawn out from both sides of the package in an I-shape and the center distance is 1.27mm. The mounting area is smaller than the SOP. Hitachi has adopted this package in analog ICs (motor drive ICs). Number of pins: 26.
65.SOIC (small out-line integrated circuit)
Another name for SOP (see SOP). Many semiconductor manufacturers abroad use this name.
66.SOJ (Small Out-Line J-Leaded Package)
Small J-lead package. One of the surface mount packages. The pins lead from both sides of the package and are J-shaped downwards, hence the name. Usually made of plastic, most of them are used for memory LSI circuits such as DRAM and SRAM, but most of them are DRAM. Many DRAM devices packaged in SO J are mounted on SIMM. The center distance of the pins is 1.27mm, and the number of pins is from 20 to 40 (see SIMM).
67.SQL (Small Out-Line L-leaded package)
The name used for the SOP in accordance with JEDEC (United States Electronic Equipment Engineering Council) standards (see SOP).
68.SONF (Small Out-Line Non-Fin)
No heat sink SOP. Same as usual SOP. In order to show the difference of no heat sink in the power IC package, a NF (non-fin) mark has been intentionally added. The name adopted by some semiconductor manufacturers (see SOP).
69.SOF (small Out-Line package)
Small outline package. One of the surface mount packages, the pins lead out from both sides of the package into a seagull wing shape (L-shaped). Materials are plastic and ceramic. Also called SOL and DFP.
In addition to memory LSIs, SOPs are also widely used in circuits such as ASSPs that are not very large. In areas where the input and output terminals do not exceed 10 to 40, SOP is the most popular surface mount package. The center distance of the pins is 1.27mm, and the number of pins ranges from 8 to 44.
In addition, SOPs with a pin center distance of less than 1.27mm are also called SSOPs; SOPs with an assembly height of less than 1.27mm are also called TSOPs (see SSOP, TSOP). There is also a SOP with a heat sink.
70.SOW (Small Outline Package (Wide-Jype))
Wide body SOP. The name adopted by some semiconductor manufacturers.
71.COB (Chip On Board)
The IC die is fixed on the printed circuit board by bonding. That is, the chip is directly adhered to the PCB, and wire bonding is used to achieve the electrical connection between the chip and the PCB and then encapsulated with black plastic. The key technology of COB is Wire Bonding (commonly known as wire bonding) and Molding (sealing molding), which refers to the process of packaging bare circuit chips (IC Chips) to form electronic components. ICs are manufactured by bonding wires Bonding, Flip Chip, or Tape Automatic Bonding (TAB) and other technologies extend its I / O through the package's wiring.
72.COG (Chip on Glass)
COG (Chip on Glass) packaging technology is becoming increasingly practical in the world. Packaging technology that greatly affects the development of liquid crystal display (LCD) technology.

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