What is a Field Effect Transistor?

Field Effect Transistor (FET) is short for Field Effect Transistor. There are two main types: junction FET (JFET) and metal-oxide semiconductor FET (MOS-FET). The majority carrier participates in conduction and is also called a unipolar transistor. It belongs to a voltage-controlled semiconductor device. It has the advantages of high input resistance (10 ⁷ 10 ¹⁵ ), low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown, wide safe working area, etc., and has now become a bipolar transistor and power. A strong contender for transistors.

A field effect transistor (FET) is a semiconductor device that uses the electric field effect of the control input loop to control the output loop current and is named after it.

Because it only conducts by the majority of carriers in the semiconductor, it is also called a unipolar transistor .

FET is English for Field Effect Transistor, which is abbreviated as FET. ^[1]

Chinese name: FET
Foreign name: Field Effect Transistor
nickname: Field effect transistor or mos tube

expression: FET
Applied discipline: physical
Scope of application: Electricity

FET characteristics

FET Compared with bipolar transistors , FETs have the following characteristics.

(1) The field effect transistor is a voltage control device, which controls I _D (drain current) through V _GS (gate-source voltage);

(2) The current at the control input of the FET is very small, so its input resistance (10 ⁷ 10 ¹² ) is very large.

(3) It uses most carriers to conduct electricity, so its temperature stability is better;

(4) The voltage amplification factor of the amplifier circuit formed by it is smaller than the voltage amplification factor of the amplifier circuit formed by the triode;

(5) The radiation resistance of the field effect tube is strong;

(6) Because it does not have shot noise caused by the electronic diffusion of chaotic motion, the noise is low.

How FETs work

In a word, the working principle of the field effect transistor is "the ID flowing through the channel between the drain and the source, and the ID of the reverse-biased gate voltage formed by the pn junction between the gate and the channel. More specifically, the width of the ID flow path, that is, the cross-sectional area of the channel, is controlled by the change in the reverse bias of the pn junction, which results in the expansion of the depletion layer. In the unsaturated region of VGS = 0, the expansion of the indicated transition layer is not very large. According to the electric field of VDS applied between the drain and source, some electrons in the source region are pulled by the drain, that is, from the drain. A current ID flows to the source. The transition layer extending from the gate to the drain forms a part of the channel as a blocking type, and the ID is saturated. This state is called pinch off. This means that the transition layer blocks part of the channel, not that the current is cut off.

In the transition layer, because there is no free movement of electrons and holes, it has almost insulating properties under ideal conditions, and it is usually difficult for current to flow. However, the electric field between the drain and the source at this time is actually that the two transition layers contact the drain and the gate near the lower part, and the high-speed electrons pulled by the drift electric field pass through the transition layer. ID saturation occurs due to the almost constant strength of the drifting electric field. Secondly, VGS changes to a negative direction, letting VGS = VGS (off), at this time, the transition layer becomes a state covering the entire area. And most of the electric field of the VDS is applied to the transition layer, and the electric field that pulls the electrons in the direction of drift is only a short part near the source, which makes the current unable to flow.

MOS field effect tube power switch circuit

MOS field effect transistors are also called metal oxide semiconductor field effect transistors (MetalOxideSemiconductor FieldEffect Transistor, MOSFET). It generally has two types of depletion and enhanced. Enhanced MOS field effect transistors can be divided into NPN type PNP type. The NPN type is usually called an N-channel type, and the PNP type is also called a P-channel type. For an N-channel FET, its source and drain are connected to an N-type semiconductor, and for a P-channel FET, its source and drain are connected to a P-type semiconductor. The output current of the FET is controlled by the input voltage (or electric field). It can be considered that the input current is very small or there is no input current, which makes the device have a high input impedance, which is also what we call a FET s reason.

When a forward voltage is applied to the diode (P terminal is connected to the positive electrode and N terminal is connected to the negative electrode), the diode is turned on, and a current is passed through its PN junction. This is because when the P-type semiconductor terminal has a positive voltage, the negative electrons in the N-type semiconductor are attracted to the P-type semiconductor terminal to which a positive voltage is applied, and the positrons in the P-type semiconductor terminal are directed toward the N-type semiconductor terminal. Movement, thereby forming a conducting current. Similarly, when a reverse voltage is applied to the diode (P terminal is connected to the negative electrode and N terminal is connected to the positive electrode), a negative voltage is generated at the P-type semiconductor terminal. Type semiconductor terminal, the electrons do not move, no current flows through the PN junction, and the diode is turned off. When there is no voltage at the gate, it can be known from the previous analysis that no current flows between the source and the drain, and the FET is in the off state at this time (Figure 7a). When a positive voltage is applied to the gate of the N-channel MOS field effect transistor, due to the effect of the electric field, the negative electrons of the source and drain of the N-type semiconductor are attracted to the gate, but because The blocking of the oxide film causes the electrons to collect in the P-type semiconductor between the two N channels (see FIG. 7b), thereby forming a current, and conducting between the source and the drain. It can be imagined that there is a trench between two N-type semiconductors, and the establishment of the gate voltage is equivalent to building a bridge between them. The size of the bridge is determined by the gate voltage.

C-MOS FET (Enhanced MOS FET)

The circuit uses an enhanced P-channel MOS FET and an enhanced N-channel MOS FET. When the input terminal is at a low level, the P-channel MOS field effect transistor is turned on, and the output terminal is connected to the positive electrode of the power supply. When the input terminal is high, the N-channel MOS field effect transistor is turned on, and the output terminal is connected to the power ground. In this circuit, the P-channel MOS field effect transistor and the N-channel MOS field effect transistor always work in opposite states, and their phase input ends and output ends are opposite. In this way we can get a larger current output. At the same time, due to the influence of leakage current, the gate voltage has not yet reached 0V, and usually when the gate voltage is less than 1 to 2V, the MOS field effect transistor is turned off. Different FETs have slightly different turn-off voltages. Because of this, the circuit will not cause a short circuit in the power supply because the two tubes are turned on at the same time.

FET classification

FETs are divided into two categories: junction FETs (JFETs) and insulated gate FETs (MOS transistors) .

There are two types of N-channel and P-channel according to the channel material type and the insulated gate type. According to the conduction method: depletion type and enhanced type, the junction field effect tube is a depletion type. There are depleted and enhanced.

Field-effect transistors can be divided into junction field-effect transistors and MOS field-effect transistors, and MOS field-effect transistors are further divided into four categories: N-channel depletion and enhancement; P-channel depletion and enhancement.

Junction FET (JFET)

1. Classification of junction field effect tubes: There are two types of structure of junction field effect tubes, they are N-channel junction field effect tube and P-channel junction field effect tube.

A junction field effect transistor also has three electrodes, which are: a gate; a drain; and a source.

Arrow of grid in circuit symbol

FET The direction can be understood as the forward conduction direction of the two PN junctions.

2. The working principle of a junction field-effect transistor (taking an N-channel junction field-effect transistor as an example), the structure and symbol of the N-channel structure field-effect transistor, because the carriers in the PN junction have been exhausted, so PN is basically non-conductive and forms a so-called depletion region. When the drain power supply voltage ED is constant, the more negative the gate voltage, the thicker the depletion region formed at the PN junction interface. The narrower the conductive channel is, the smaller the drain current ID is; on the contrary, if the gate voltage is not so negative, the channel becomes wider and the ID becomes larger, so the gate voltage EG can be used to control the change of the drain current ID. That is, the FET is a voltage control element.

IGBT

1. Classification of insulated gate field effect tubes (MOS tubes): There are also two structural forms of insulated gate field effect tubes, which are N-channel type and P-channel type. No matter what channel they are, they are divided into two types: enhanced and depleted.

2. It is composed of metal, oxide and semiconductor, so it is also called metal-oxide-semiconductor field effect tube, referred to as MOS field effect tube for short.

3. The working principle of insulated gate field effect tube (taking N-channel enhancement type MOS field effect tube as an example), it uses UGS to control the amount of "inductive charge" to change the conductive groove formed by these "inductive charge" Channel conditions, and then achieve the purpose of controlling the drain current. When manufacturing the tube, a large number of positive ions appear in the insulating layer through the process, so more negative charges can be induced on the other side of the interface. These negative charges turn on the N region of the high-permeability impurities and form a conductive trench Channel, even when VGS = 0, there is a large drain current ID. When the gate voltage is changed, the amount of charge induced in the channel is also changed, and the width of the conductive channel is also changed accordingly. Therefore, the drain current ID changes with the change of the gate voltage.

There are two kinds of working methods of FETs: those with larger drain current when the gate voltage is zero are called depletion type; when the gate voltage is zero, the drain current is also zero, and a certain gate voltage must be added after Only the drain current is called enhanced.

FET effect

1. FET can be used for amplification. Because the input impedance of the FET amplifier is very high, the coupling capacitor can have a smaller capacity, and it is not necessary to use an electrolytic capacitor.

2. The high input impedance of the FET is very suitable for impedance transformation. Commonly used in the input stage of a multi-stage amplifier for impedance transformation.

3. The FET can be used as a variable resistor.

4. The FET can be conveniently used as a constant current source.

5. The FET can be used as an electronic switch.

FETs

MOS field effect tube

It is a metal-oxide-semiconductor field-effect transistor, which is abbreviated as MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor), and is an insulated gate type. Its main feature is a silicon dioxide insulation layer between the metal gate and the channel, so it has a high input resistance (up to 1015). It is also divided into N-channel tubes and P-channel tubes. Usually, the substrate (substrate) and the source S are connected together. According to different conduction methods, MOSFETs are divided into enhanced and depleted types. The so-called enhanced type means that when VGS = 0, the tube is in a cut-off state. After adding the correct VGS, most carriers are attracted to the gate, thereby enhancing the carriers in this area and forming a conductive channel . The depletion type means that a channel is formed when VGS = 0, and when the correct VGS is added, most carriers can flow out of the channel, thus depleting the carriers and turning the tube to turn off.

Taking the N channel as an example, two source diffusion regions N + and drain diffusion regions N + with a high doping concentration are formed on a P-type silicon substrate, and a source S and a drain D are respectively drawn. The source and the substrate are internally connected, and the two always maintain an equipotential. When the drain is connected to the positive pole of the power supply, the source is connected to the negative pole of the power supply, and VGS = 0, the channel current (ie, drain current) ID = 0. As VGS gradually increases and is attracted by the positive gate voltage, negatively charged minority carriers are induced between the two diffusion regions, forming an N-type channel from the drain to the source. When VGS is greater than the tube When the turn-on voltage VTN (generally about + 2V), the N-channel tube starts to conduct, forming a drain current ID.

MOS field effect tube

VMOS FET

VMOS field effect tube (VMOSFET) is referred to as VMOS tube or power field effect tube, which is called V-groove MOS field effect tube. It is a newly developed high-efficiency, power switching device after MOSFET. It not only inherits the high input impedance (108W) of the MOS field effect transistor and the small driving current (about 0.1A), it also has high withstand voltage (up to 1200V), large working current (1.5A 100A), output High power (1 ~ 250W), good linearity of transconductance, fast switching speed, etc. It is precisely because it combines the advantages of the electron tube and the power transistor, so it is widely used in voltage amplifiers (the voltage amplification can reach thousands of times), power amplifiers, switching power supplies and inverters.

As is known to all, the gate, source, and drain of a traditional MOS FET are mostly on a chip that is approximately at the same horizontal plane, and its operating current basically flows in the horizontal direction. VMOS tubes are different, with two major structural features: first, the metal gate uses a V-groove structure; second, it has vertical conductivity. Since the drain is drawn from the back of the chip, the ID does not flow along the chip horizontally, but starts from the heavily doped N + region (source S), flows into the lightly doped N-drift region through the P channel, and finally reaches vertically downward. Drain D. Since the flow cross-sectional area is increased, a large current can be passed. Because there is a silicon dioxide insulating layer between the gate and the chip, it still belongs to an insulated gate MOS field effect transistor.

Advantages of using FETs

VMOS FET The FET is a voltage control element and the transistor is a current control element.

FET In the case where only less current is allowed to be taken from the signal source, a field effect transistor should be used; while in the condition that the signal voltage is low and more current is allowed to be taken from the signal source, a transistor should be used. The field effect tube conducts electricity by using majority carriers, so it is called a unipolar device, and the transistor conducts electricity by using both majority carriers and minority carriers, and is called a bipolar device.

The source and drain of some field-effect transistors can be used interchangeably, and the gate voltage can also be positive or negative. The flexibility is better than that of triodes.

FETs can work under very low current and low voltage conditions, and its manufacturing process can easily integrate many FETs on a silicon chip, so FETs have been obtained in large-scale integrated circuits. Wide application.

FET comparison

The respective application characteristics of FET and transistor

1. The source s, gate g, and drain d of the field-effect transistor correspond to the emitter e, the base b, and the collector c of the transistor, respectively, and their functions are similar.

2. The field-effect transistor is a voltage-controlled current device. The iD is controlled by vGS, and its amplification factor gm is generally small, so the amplification effect of the field-effect transistor is poor; the transistor is a current-controlled current device, and iC is controlled by iB (or iE).

FET 3. The gate of the field-effect transistor takes almost no current (ig & raquo; 0); the base always draws a certain current when the transistor is operating. Therefore, the input resistance of the gate of the field effect transistor is higher than that of the triode.

4. The field effect tube is composed of multiple electrons to conduct electricity; the triode has multiple electrons and minority carriers to conduct electricity, and the minority electron concentration is greatly affected by factors such as temperature and radiation. Therefore, the field effect transistor has better temperature stability and resistance than the transistor. Strong radiation ability. FETs should be used when the environmental conditions (temperature, etc.) vary widely.

5. When the source metal and the substrate are connected together, the field effect tube can be used interchangeably with little change in characteristics; while the collector and emitter of the triode are used interchangeably, the characteristics are very different. Larger, the value will decrease a lot.

6. The noise factor of the field effect tube is very small. It is necessary to use the field effect tube in the input stage of the low noise amplifier circuit and in the circuit that requires high signal to noise.

7. The field effect transistor and the transistor can form various amplifying circuits and switching circuits, but because of the simple manufacturing process, the former has the advantages of less power consumption, good thermal stability, and wide operating power supply voltage range, it is widely used in large Scale and VLSI.

8. The on-resistance of the triode is large, and the on-resistance of the field-effect transistor is small, only a few hundred milliohms. On current electrical devices, field-effect transistors are generally used as switches, and his efficiency is relatively high.

Comparison of FET and Bipolar Transistor

The field effect tube is a voltage control device, and the gate basically does not take current, while the transistor is a current control device, and the base must take a certain current. Therefore, when the rated current of the signal source is extremely small, a field effect tube should be selected.
The FET is multi-electron conductive, and both carriers of the transistor are involved in the conduction. Because the concentration of minority carrier is sensitive to external conditions such as temperature and radiation, it is more appropriate to use a field effect tube for occasions with large environmental changes.
In addition to transistors, which can be used as amplifier devices and controllable switches, they can also be used as voltage-controlled variable linear resistors.
The source and drain of the FET are symmetrical in structure and can be used interchangeably. The gate-source voltage of the depletion MOS tube can be positive or negative. Therefore, the use of FETs is more flexible than transistors.

Model name of FET

There are two naming methods.

The first naming method is the same as the bipolar triode. The third letter J represents a junction field effect transistor, and O represents an insulated gate field effect transistor. The second letter represents the material, D is P-type silicon, the inversion layer is N-channel; C is N-type silicon P-channel. For example, 3DJ6D is a junction P-channel field effect transistor, and 3DO6C is an insulated gate N-channel field effect transistor.

The second naming method is CS ×× # , where CS stands for FET, ×× represents the serial number of the model, and # represents the different specifications of the same model with letters. For example CS14A, CS45G and so on.

Main parameters of FET

DC parameters of FET

The saturation drain current IDSS can be defined as: when the voltage between the gate and source is equal to zero, and the drain

FET When the voltage between the source and the pinch-off voltage is greater, the corresponding drain current.

The pinch-off voltage UP can be defined as: UGS required when ID is reduced to a small current when UDS is constant.

Turn-on voltage UT can be defined as: UGS required when ID reaches a certain value when UDS is constant.

FET AC parameters

AC parameters can be divided into two parameters: output resistance and low-frequency transconductance. The output resistance is generally between tens of thousands of ohms and hundreds of thousands of ohms. It can reach 100mS or even higher.

Low-frequency transconductance gm describes the control effect of gate and source voltage on drain current.

The capacitance between the three electrodes of the inter-electrode capacitance field-effect tube. The smaller the value, the better the performance of the tube.

MOSFET limit parameters

The maximum drain current refers to the upper limit of the drain current allowed during normal operation of the tube.

The maximum dissipated power is the power in the tube, which is limited by the maximum working temperature of the tube.

The maximum drain-source voltage is the voltage that occurs when avalanche breakdown occurs and the drain current starts to rise sharply.

The maximum gate-source voltage refers to the voltage value when the reverse current between the gate-source starts to increase sharply.

In addition to the above parameters, there are other parameters such as inter-electrode capacitance and high-frequency parameters.

Drain and source breakdown voltage When the drain current rises sharply, UDS at the time of avalanche breakdown occurs.

When the gate breakdown voltage junction field effect transistor works normally, the PN junction between the gate and the source is in a reverse bias state. If the current is too high, a breakdown phenomenon will occur.

The main parameters of concern when using are:

1. IDSSsaturated drain-source current. It refers to the drain-source current in the junction or depletion type insulated gate field effect transistor when the gate voltage UGS = 0.

2. UPPinch off voltage. It refers to the gate voltage of the junction or depletion type insulated gate field effect transistor immediately after the drain-source is turned off.

3. UTOpening voltage. It refers to the gate voltage when the drain-source is just turned on in the reinforced insulated gate field effect transistor.

4. gMtransconductance. It is the gate-to-source voltage UGSthe ability to control the drain current ID, that is, the ratio of the change in the drain current ID to the change in the gate-source voltage UGS. gM is an important parameter to measure the amplification ability of the FET.

5. BUDSDrain-source breakdown voltage. It refers to the maximum drain-source voltage that the field effect tube can withstand when the gate-source voltage UGS is constant. This is a limit parameter. The working voltage applied to the FET must be less than BUDS.

6. PDSMMaximum power dissipation. It is also a limit parameter, which refers to the maximum drain-source dissipation power allowed when the performance of the FET is not deteriorated. When used, the actual power consumption of the FET should be less than PDSM and leave a certain margin. 7. IDSMMaximum drain-source current. It is a limit parameter, which refers to the maximum current allowed between the drain and the source when the field effect tube works normally. The working current of the FET should not exceed IDSM.

FET measurement method

Resistance measuring electrode

According to the phenomenon that the forward and reverse resistance values of the PN junction of the field effect tube are different, three of the junction field effect tube can be identified.

FET electrode. Specific method: Dial the multimeter to R × 1k, and select two electrodes, and measure the forward and reverse resistance values respectively. When the forward and reverse resistance values of two electrodes are equal and are several thousand ohms, the two electrodes are the drain D and the source S, respectively. Because for the junction FET, the drain and source are interchangeable, the remaining electrode must be the gate G. You can also touch the black test lead (the red test lead of the multimeter) to one electrode at will, and the other test lead to contact the other two electrodes in order to measure the resistance value. When the resistance values measured twice are approximately equal, the electrode contacted by the black test lead is the gate electrode, and the remaining two electrodes are the drain electrode and the source electrode, respectively. If the resistance values measured twice are very large, it means that the PN junction is reversed, that is, they are all reverse resistances. It can be judged that they are P-channel field effect transistors, and the black test lead is connected to the gate. The resistance values are very small, indicating that it is the forward PN junction, that is, the forward resistance, which is determined to be an N-channel field effect transistor, and the black test lead is also connected to the gate. If the above situation does not occur, the black and red test leads can be replaced and tested according to the above method until the grid is identified.

Good or bad resistance measurement

The resistance measurement method uses a multimeter to measure the resistance between the source and drain of the FET, the gate and source, the gate and drain, and the gate G1 and G2. The resistance value is the same as the resistance value indicated in the field effect tube manual. Whether it is consistent or not to judge the quality of the tube. Specific method: First set the multimeter to R × 10 or R × 100, and measure the resistance between the source S and the drain D, usually in the range of tens of ohms to thousands of ohms (as can be seen in the manual, various models , The resistance value of each tube is different), if the measured resistance value is greater than the normal value, it may be due to poor internal contact; if the measured resistance value is infinite, it may be an internal disconnection. Then put the multimeter in the R × 10k range, and then measure the resistance between the gates G1 and G2, between the gate and the source, and between the gate and the drain. When the resistance values are measured to be infinite, then It indicates that the tube is normal; if the above resistance values are too small or are channels, it means that the tube is bad. It should be noted that if the two grids are broken in the tube, the component replacement method can be used for detection.

Measuring magnification

The specific method using the inductive signal method: Use the R × 100 range of the multimeter resistance, connect the red test lead to the source S, and the black test lead to the drain D, and apply a 1.5V power supply voltage to the field effect tube. Resistance between electrodes. Then, hold the grid G of the junction field effect transistor by hand, and add the induced voltage signal of the human body to the grid. In this way, due to the amplification effect of the tube, both the drain-source voltage VDS and the drain current Ib must be changed, that is, the resistance between the drain-source has changed, and thus the watch hand can be observed to have a large swing. If the pin of the grid pin is small, it means that the tube has a poor magnifying ability; if the pin is big, it means that the tube has a large magnifying ability; if the pin does not move, the tube is broken.

FET According to the above method, use the R × 100 range of the multimeter to measure the junction field effect tube 3DJ2F. First open the G-pole of the tube, and measure the drain-source resistance RDS to be 600. After pinching the G-pole with your hand, the meter will swing to the left. The indicated resistance RDS will be 12k. , And has a larger magnification ability.

When using this method, a few points need to be explained: First, when testing the FET to hold the grid with your hand, the multimeter needle may swing to the right (resistance value decreases) or to the left (increased resistance value). This is because the AC voltage induced by the human body is high, and the operating point of different field effect tubes when measured with a resistance file may be different (either in the saturated region or in the unsaturated region). Experiments show that the RDS of most tubes increases That is, the hand is swinging to the left; the RDS of a few tubes is reduced, which makes the hand to swing to the right. However, regardless of the direction of the hand's swing, as long as the hand's swing is large, it means that the tube has a large magnification ability. Second, this method is also applicable to MOS FETs. However, it should be noted that the input resistance of the MOS field effect transistor is high, and the induced voltage allowed by the grid G should not be too high, so do not directly pinch the grid with your hand. It must be used to hold the insulating handle of a screwdriver and touch it with a metal rod. Touch the grid to prevent the body's induced charge from directly adding to the grid and causing grid breakdown. Third, each measurement should be shorted between GS electrodes. This is because the GS junction capacitor will be charged with a small amount of charge, which establishes the VGS voltage, which may cause the hands to move when the measurement is performed again. It is only necessary to discharge the short-circuited charge between the GS electrodes.

Identification of unmarked tubes

First, use the method of measuring resistance to find two pins with resistance value, that is, source S and drain D. The rest

FET The two pins are a first gate G1 and a second gate G2. Record the resistance value between the source S and the drain D measured with two test leads first, and then measure the test leads again, and then record the measured resistance values. Measure the resistance with a larger value twice, black test leads. The electrode connected is the drain D; the red test lead is connected to the source S. The S and D poles identified in this way can also be verified by estimating the magnification ability of the tube, that is, the black test pen with large magnification is connected to the D pole; the red test pen is grounded to the S pole. The test results of all methods should be the same. After the positions of the drain D and the source S are determined, the circuit is installed according to the corresponding positions of D and S. Generally, G1 and G2 will also be aligned in order. This determines the positions of the two gates G1 and G2. Thus, the order of the D, S, G1, and G2 pins is determined.

Determine the size of the transconductance

Measure the change of the reverse resistance value to determine the size of the transconductance. When measuring the transconductance performance of the VMOSV channel enhanced field effect tube, you can use a red test lead to connect the source S and a black test lead to the drain D. This is equivalent to A reverse voltage is applied across the drain. At this time, the grid is open and the reverse resistance of the tube is very unstable. The ohm range of the multimeter is selected in the high resistance range of R × 10k. At this time, the voltage in the meter is higher. When you touch the grid G with your hand, you will find that the reverse resistance value of the tube changes significantly. The larger the change, the higher the transconductance value of the tube; if the transconductance of the tube under test is small, use this method to measure At this time, the reverse resistance does not change much.

FET test method

Knotted Field Pin Identification

The gate of the FET is equivalent to the base of the transistor, and the source and drain correspond to the emitter and collector of the transistor, respectively.

FET pole. Set the multimeter to R × 1k, and use two test leads to measure the forward and reverse resistance between each two pins. When the positive and negative resistances between two pins are equal, both are several K, then these two pins are the drain D and the source S (interchangeable), and the remaining one is the gate G . For a junction FET with 4 pins, the other pole is the shield pole (grounded during use).

Decision gate

Use a multimeter black test pen to touch one electrode of the tube, and a red test pen to touch the other two electrodes. If the resistance values measured twice are very large, it means that they are reverse resistances. The tube is an N-channel field effect tube, and the black test lead is also connected to the grid. The manufacturing process determines that the source and drain of the FET are symmetrical and can be used interchangeably without affecting the normal operation of the circuit, so there is no need to distinguish them. The resistance between the source and the drain is about several thousand ohms.

Note that this method cannot be used to determine the gate of an insulated gate field effect transistor. Because the input resistance of this type of tube is very high, and the inter-electrode capacitance between the gate and source is very small, as long as there is a small amount of charge during the measurement, a high voltage can be formed on the inter-electrode capacitance, and the tube is easily damaged.

Estimating Magnification Capability

Set the multimeter to R × 100, the red test lead is connected to the source S, and the black test lead is connected to the drain D, which is equivalent to adding a 1.5V power supply voltage to the field effect tube. At this time, the hands indicate the resistance value between the DS electrodes. Then pinch the grid G with your fingers,

FET It is applied to the gate as an input signal. Due to the magnification of the tube, both UDS and ID will change, which is also equivalent to the change in DS inter-electrode resistance. It can be observed that the hand has a large swing. If the hand movement is small when pinching the grid, it means that the tube's magnification ability is weak; if the hand doesn't move, the pipe is damaged. Because the 50Hz AC voltage induced by the human body is high, and the working point of different field effect tubes when measuring with a resistance file may be different, the hand may swing to the right or swing to the left when pinching the grid with your hands. The RDS of a few tubes decreases, which causes the hands to swing to the right, and the RDS of most tubes increases, and the hands swing to the left. Regardless of the swing direction of the hand, as long as it can be clearly swung, it means that the tube has a magnifying ability.

This method is also applicable to measuring MOS tubes. In order to protect the MOS field-effect tube, it is necessary to hold the screw handle's insulating handle with a hand and touch the grid with a metal rod to prevent the human body from directly inducing charges on the grid and damaging the tube.

After each measurement of the MOS tube, a small amount of charge will be charged on the GS junction capacitor, and the voltage UGS will be established. Then, when the measurement is performed, the hands may not move. At this time, short the GS electrode.

FET product characteristics

(1) Transfer characteristics: The control effect of gate voltage on drain current is called transfer characteristics.

(2) Output characteristics: The relationship between UDS and ID is called output characteristics.

(3) Amplification effect of the junction field effect tube: The amplification effect of the junction field effect tube generally refers to a voltage amplification effect.

Electrical characteristics of FET

The main differences between FETs and transistors in electrical characteristics are as follows:

SMD FET

FET 1: The field effect tube is a voltage control device. The conductivity of the tube depends on the gate voltage. The transistor is a current control device, and the conductivity of the tube depends on the magnitude of the base current. 2: The static volt-ampere characteristics of the field-effect transistor drain-source use the gate voltage UGS as a parameter, and the transistor output characteristic curve uses the base current Ib as a parameter.

3: The relationship between the field effect tube current IDS and the gate UGS is determined by the transconductance Gm, and the relationship between the transistor currents Ic and Ib is determined by the amplification factor . In other words, the amplification capability of the FET is measured in Gm, and the amplification capability of the transistor is measured in .

4: The input impedance of the FET is very large, and the input current is extremely small; the input impedance of the transistor is very small, and the input current is large when conducting.

5: Generally, the power of the FET is small, and the power of the transistor is large.

FET parameter symbol

Cds --- drain-source capacitance	Cdu --- Drain-Substrate Capacitance	Cgd --- gate-drain capacitance	Cgs --- gate-source capacitance	Ciss --- gate short-circuit common source input capacitance	Coss --- gate short-circuit common source output capacitor
Crss --- gate short-circuit common source reverse transmission capacitor	D --- duty cycle (duty factor, external circuit parameters)	di / dt --- current rise rate (external circuit parameters)	dv / dt --- voltage rise rate (external circuit parameters)	ID --- drain current (DC)	IDM --- drain pulse current
ID (on) --- on-state drain current	IDQ --- Static Drain Current (RF Power Tube)	IDS --- drain-source current	IDSM --- Maximum drain-source current	IDSS --- Drain current when gate-source short circuit	IDS (sat) --- channel saturation current (drain-source saturation current)
IG --- gate current (DC)	IGF --- forward gate current	IGR --- Reverse Gate Current	IGDO --- When the source is open, the gate current is cut off	IGSO --- off-gate current when open-drain	IGM --- Gate Pulse Current
IGP --- gate peak current	IF --- diode forward current	IGSS --- cut-off gate current when drain short circuit	IDSS1 --- the first drain-source saturation current of the first tube	IDSS2 --- Secondary tube drain-source saturation current	Iu --- substrate current
Ipr --- peak current pulse (external circuit parameters)	gfs --- forward transconductance	Gp --- power gain	Gps --- common source neutral and high frequency power gain	GpG --- common grid neutralization and high frequency power gain	GPD --- common drain neutral high frequency power gain
ggd --- gate leakage conductance	gds --- drain-source conductance	K --- offset voltage temperature coefficient	Ku --- transmission coefficient	L --- load inductance (external circuit parameters)	LD --- Drain inductance
Ls --- source inductance	rDS --- drain-source resistance	rDS (on) --- drain-source on-resistance	rDS (of) --- drain-source off-state resistance	rGD --- gate leakage resistance	rGS --- gate source resistance
Rg --- external resistance of the gate (external circuit parameters)	RL --- load resistance (external circuit parameters)	R (th) jc --- junction-to-case thermal resistance	R (th) ja --- junction ring thermal resistance	PD --- Drain Dissipated Power	PDM --- Maximum allowable drain power
PIN--input power	POUT --- output power	PPK --- Pulse power peak (external circuit parameters)	to (on) --- delay time	td (off) --- off delay time	ti --- rise time
ton --- on time	toff --- off time	tf --- fall time	trr --- Reverse Recovery Time	Tj --- junction temperature	Tjm --- Maximum allowable junction temperature
Ta --- Ambient temperature	Tc --- case temperature	Tstg --- storage temperature	VDS --- Drain-Source Voltage (DC)	VGS --- Gate Source Voltage (DC)	VGSF--forward gate-source voltage (DC)
VGSR --- Reverse Gate-Source Voltage (DC)	VDD --- drain (DC) power supply voltage (external circuit parameters)	VGG --- grid (DC) power supply voltage (external circuit parameters)	Vss --- source (DC) power supply voltage (external circuit parameters)	VGS (th) --- opening voltage or valve voltage	V BR DSS--Drain-source breakdown voltage
V BR GSS --- Gate-source breakdown voltage when drain-source short	VDS (on) --- drain-source on-state voltage	VDS (sat) --- drain-source saturation voltage	VGD --- Gate Drain Voltage (DC)	Vsu --- source substrate voltage (DC)	VDu --- drain substrate voltage (DC)
VGu --- gate substrate voltage (DC)	Zo --- internal resistance of driving source	--- drain efficiency (RF power tube)	Vn --- noise voltage	aID --- Drain current temperature coefficient	ards --- temperature coefficient of drain-source resistance

Note for FETs

(1) In order to use the field effect tube safely, the design of the line must not exceed the limit values of the tube's dissipation power, maximum drain-source voltage, maximum gate-source voltage, and maximum current.

(2) When using various types of field effect transistors, they must be connected to the circuit strictly according to the required bias, and the polarity of the field effect tube bias must be observed. If the junction between the source and drain of the junction field effect transistor gate is a PN junction, the gate of the N-channel transistor cannot be biased positively; the gate of the P-channel transistor cannot be biased negatively

FET Press, wait. (3) Due to the extremely high input impedance of MOS field-effect transistors, the lead pins must be short-circuited during transportation and storage. They must be packaged with metal shields to prevent external induced potential from breaking the grid. Pay particular attention to the fact that MOS field-effect tubes cannot be put in plastic boxes. It is best to put them in metal boxes during storage. At the same time, pay attention to the moisture resistance of the tubes.

(4) In order to prevent the induction breakdown of the MOSFET grid, all test instruments, workbenches, soldering irons, and the line itself must be well grounded; when the pins are soldered, the source is soldered first; before connecting to the circuit All lead ends of the tube should be short-circuited to each other, and the short-circuiting material should be removed only after welding. When removing the tube from the component rack, you should ensure that the human body is grounded in a proper way, such as using a ground ring. Of course, if you can Using an advanced gas-heated electric soldering iron, it is more convenient to weld the field effect tube and ensure safety; when the power is not turned off, the tube must not be inserted into or pulled out of the circuit. The above safety measures must be paid attention to when using the field effect tube.

(5) When installing the field effect tube, pay attention to the location of the installation to avoid as close as possible to the heating element; in order to prevent the vibration of the tube, it is necessary to fasten the tube housing; when the pin lead is bent, it should be larger than the root size by 5 mm Proceed to prevent the pins from being broken and cause air leakage.

(6) When using a VMOS tube, a suitable heat sink must be added. Taking VNF306 as an example, the maximum power can reach 30W after a 140 × 140 × 4 (mm) radiator is installed on the tube.

(7) After the multi-tubes are connected in parallel, the high-frequency characteristics of the amplifier are deteriorated due to the corresponding increase in the inter-electrode capacitance and the distributed capacitance, and the high-frequency parasitic oscillation of the amplifier is easily caused by feedback. For this reason, generally no more than four tubes are connected in parallel, and a parasitic resistance is connected in series to the base or grid of each tube.

(8) The grid-source voltage of the junction FET cannot be reversed and can be stored in an open circuit state. When the insulated gate FET is not in use, because its input resistance is very high, the electrodes must be shorted to avoid The external electric field caused the tube to be damaged.

FET (9) When soldering, the outer shell of the soldering iron must be equipped with an external ground wire to prevent damage to the pipe due to the electrification of the soldering iron. For a small amount of soldering, you can also heat the electric iron and unplug it or cut off the power and solder. Especially when welding an insulated gate field effect tube, the welding must be performed in the order of source-drain-gate and power off welding.

(10) When soldering with a 25W electric soldering iron, it should be fast. If soldering with a 45 75W electric soldering iron, use tweezers to clamp the root of the pin to help heat dissipation. The junction field effect tube can be used to check the quality of the tube qualitatively (check the forward and reverse resistance of each PN junction and the resistance between the drain and source), but the insulated gate field effect tube cannot be checked by a multimeter, and a tester must be used. , And you can only remove the short circuit of each electrode after connecting to the tester. When removing, it should be short-circuited before removing, the key is to avoid the gate floating.

When it is used in a place with high input impedance, moisture-proof measures must be taken to prevent the input resistance of the field-effect transistor from being lowered due to temperature influence. If a four-lead FET is used, its substrate leads should be grounded. The ceramic packaged sesame tube has light-sensitive properties, so care should be taken to avoid light.

For power FETs, good heat dissipation conditions are required. Because power FETs are used under high load conditions, sufficient heat sinks must be designed to ensure that the case temperature does not exceed the rated value, so that the device can work stably and reliably for a long time.

In short, to ensure the safe use of field-effect transistors, there are various matters to be noted, and the various security measures to be taken. The vast number of professional and technical personnel, especially the majority of electronic enthusiasts, must proceed according to their actual conditions , Take practical measures to use the field effect tube safely and effectively.

Field application field

A field-effect transistor (FET) is a unipolar semiconductor device that controls the magnitude of the electric field effect. The input terminal basically does not draw current or the current is very small, has the characteristics of high input impedance, low noise, good thermal stability, simple manufacturing process, etc., and is used in large-scale and ultra-large-scale integrated circuits.

With its low power consumption, stable performance, and strong radiation resistance, field effect devices have gradually replaced transistors in integrated circuits. But it is still very delicate. Although most of them have built-in protection diodes, if they are not careful, they will be damaged. So be careful in your application.

FET type

Depletion FET at standard voltage. From left to right: junction field effect transistor, polysilicon metal-oxide-semiconductor field effect tube, double gate metal-oxide-semiconductor field effect tube, metal gate metal-oxide-semiconductor field effect tube , Metal semiconductor field effect tube. Depletion layer, electron, hole, metal, insulator. Top: Source, Bottom: Drain, Left: Gate, Right: Body. Details of channel formation caused by voltage are not drawn

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The channel of a doped FET (explained below) is used to make an N-type semiconductor or a P-type semiconductor. In a depletion mode FET, the drain and source may be doped to different types to the channel. Or FETs in boost mode, they may be doped to similar types. Field-effect transistors are distinguished by different methods of insulating channels and gates. The types of FETs are:

DEPFET (Depleted FET) is a FET that is fabricated on a completely depleted substrate and is used as an inductor, amplifier, and memory. It can be used as an image (photon) sensor.

DGMOFET (Dual-gate MOSFET) is a MOSFET with two gates.

DNAFETFETDNADNA

FREDFETFast Recovery Epitaxial Diode FETFET

HEMTHigh Electron Mobility TransistorHFETheterostructure FETAlGaAs

IGBTInsulated-Gate Bipolar TransistorMOSFET200-3000MOSFET1200.

ISFETIon-Sensitive Field Effect Transistor,pH

JFETpn

MESFETMetal-Semiconductor FETJFETPNGaAs

MODFETModulation-Doped FET

MOSFET

NOMFETNanoparticle Organic Memory FET

OFETOrganic FET

1925Julius Edgar Lilienfeld1934Oskar Heil1952Junction-FETJFET1960Dawan KahngMetal-Oxide-Semiconductor Field-effect transistor, MOSFETJFET

All FETs have three ends: gate, drain, and source, which correspond to the base, collector, and emitter of the BJT. In addition to JFETs, all FETs also have a fourth terminal, called a body, base, bulk, or substrate. This fourth terminal can modulate the transistor to operation; in circuit design, the body terminal is rarely allowed to play a large role, but its existence is important when physically designing an integrated circuit. In the figure, the length L of the gate refers to the distance between the source and the drain. Width refers to the range of the transistor, which is perpendicular to the cross section in the figure. The width is usually much larger than the length. A maximum gate frequency of 1 micron is about 5 GHz, and 0.2 micron is about 30 GHz.

The names of these ends are related to their functions. The gate can be thought of as a switch that controls a physical gate. This gate can allow or block the flow of electrons by making or eliminating the channel between the source and drain. If affected by an applied voltage, electron flow will flow from the source to the drain. The body is simply the block of the semiconductor where the gate, drain, and source are located. Usually the body end is connected to the highest or lowest voltage in a circuit, which varies according to the type. The body and source are sometimes connected together, because sometimes the source is also connected to the highest or lowest voltage in the circuit. Of course, in some circuits, FETs do not have such a structure, such as cascaded transmission circuits and cascade circuits.

FET composition

FETs are composed of various semiconductors, and silicon is currently the most common. Most FETs are manufactured using traditional bulk semiconductor manufacturing techniques, using single crystal semiconductor wafers as reaction regions, or channels.

Most of the uncommon bulk materials are mainly amorphous silicon, polysilicon, or other amorphous semiconductors in thin film transistors or organic field effect transistors. Organic field-effect transistors are based on organic semiconductors and often use organic gate insulators and electrodes.