What Is Flip Chip Technology?

Flip-chip packaging technology was developed by IBM in 1960. In order to reduce costs, increase speed, and improve component reliability, FC is used in the first layer of chip and carrier bonding package. Bonding to form the shortest circuit and reduce resistance; the use of metal ball connection reduces the package size, improves electrical performance, and solves the problem of increasing the volume of the BGA to increase the number of pins.

Flip Chip Technology

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Flip-chip packaging technology was developed by IBM in 1960. In order to reduce costs, increase speed, and improve component reliability, FC is used in the first layer of chip and carrier bonding package. Bonding to form the shortest circuit and reduce resistance; the use of metal ball connection reduces the package size, improves electrical performance, and solves the problem of increasing the volume of the BGA in order to increase the number of pins.

Chinese name

Flip Chip Technology

Foreign name

FC

development company

IBM

Function

Reduce costs, increase speed, and increase reliability

Development time

1960

Features

Solve the problem of increasing the volume of BGA and increasing the volume

The earliest surface mount technology-flip-chip

In addition, FC is usually applied to CPUs with higher clock speeds or high-frequency RF to obtain better performance. Compared with traditional slow wire bonding technology, FC is more suitable for high pin count and miniaturization. , Multi-functional, high-speed trend IC products.

As electronic packaging is becoming more and more fast, smaller, and cheaper, it is required to reduce the size and increase the performance while reducing the cost. This puts the packaging industry under tremendous pressure, and the challenge is that the advantages of traditional SMD packaging technology have confirmed to us a revolution in packaging technology.

Overview

The term "flip-chip technology" includes many different approaches. Each method has many differences and applications. For example, as far as the choice of circuit board or substrate type, whether it is an organic material, ceramic material or flexible material, determines the choice of assembly materials (bump type, solder, underfill material, etc.), and to a certain extent It also determines the choice of equipment required. In the current situation, each company must decide which technology to use, which type of process components to purchase, what research and development to meet the needs of future products, and how to invest capital and operating costs. To a minimum.

The most common and appropriate method in the SMT environment is the solder paste flip chip assembly process. Even so, to ensure manufacturability, reliability, and cost goals, many changes to the technology should be considered. The widely used flip-chip method is mainly determined according to the interconnection structure. For example, compliant bump technology is implemented using gold-plated conductive polymers or polymer / elastomer bumps.

Bonding technology

The realization of the solder bump technology requires solder ball bonding (mainly using gold wire) or electroplating technology, and then the assembly is completed with a conductive isotropic adhesive. The process must not affect the integrated circuit (1C) bonding points. In this case, an anisotropic conductive film is required. Solder paste bump technology includes evaporation, electroplating, electroless plating, stencil printing, spraying, etc. Therefore, the choice of interconnection determines the bonding technology required. In general, alternative bonding technologies include: reflow bonding, thermosonic bonding, thermocompression bonding, and transient liquid phase bonding.

Each of these technologies has advantages and disadvantages and is usually driven by the application. But in terms of standard SMT process use, solder paste flip chip assembly processes are the most common and have proven to be perfectly suitable for SMT.

Solder paste flip chip assembly technology

The traditional solder paste flip-chip assembly process includes: flux coating, chip placement, solder paste reflow, and underfill. However, in order to guarantee a successful and reliable flip-chip assembly, other issues must be noted. Often, success begins with design.

The primary design considerations include solder bump and under-bump structures, with the goal of minimizing stress on interconnects and IC bond points. Known reliability models can predict problems with solder paste if the interconnect design is appropriate. Reasonable design of IC bonding point structure, passivation, polyimide opening, and under bump metallurgy (UBM) structure can achieve this goal. The design of the passivation opening must achieve the following purposes: reduce current density; reduce the area of concentrated stress; increase the life of electromigration; maximize the cross-sectional area of UBM and solder bumps.

The layout of the bump positions is another design consideration. The position of the solder bumps is as symmetrical as possible, and the identification of the orientation feature (removing a corner bump) is an exception. The layout design must also consider that the downstream slice operation will not be disturbed in any way. Placing solder bumps on the active area of an IC also depends on the electrical performance and sensitivity of the IC circuit. In addition, there are other IC design considerations, but wafer bump manufacturing companies have special IC solder joint and layout design guidelines to ensure the reliability of the bumps, thereby ensuring the reliability of the interconnection.

Major board design considerations include the size of the metal solder joints and associated solder mask openings. First, the wetting area at the plate solder joint must be maximized to form a strong bond. It must be noted that the size of the wetted area on the board should match the diameter of the UBM. This helps to form symmetrical interconnections and avoids stress at one end of the interconnect that is higher than the other end, which is a problem of stress imbalance. In fact, when designing, the method of making the solder joint diameter of the board slightly larger than the UBM diameter is usually used to focus the joint stress on one end of the circuit board instead of the weaker IC. Proper design of the solder mask opening can control the wetting area at the position of the board solder joint.

Both solder mask design and solderless mask design can be used, but the combination of these two methods is the most reliable design method. By using rectangular openings on the relevant circuit board pattern and taking the sharpness of the solder mask into consideration, an appropriate board solder joint position can be designed. If the design is unreasonable, once the assembly environment changes or the mechanical factors change, the IC will experience fatigue cracking of the solder paste. Using the underfill method can indeed greatly improve the reliability of flip chip component interconnections, but if the design guidelines are not strictly followed, the same failure mechanism will inevitably occur.

Wafer bump slicing

Solder bumps serve as mechanical, electrical, and sometimes thermal interconnections between the IC and the circuit board. In a typical flip chip device, the interconnect consists of UBM and the solder bumps themselves. UBM is bonded on the passivation layer of the wafer to protect the circuit from the external environment. In fact, UBM acts as a base for bumps. It has excellent adhesion to wafer metal and passivation materials, and acts as a solder paste diffusion layer between solder paste and IC bonding metals, while also providing an oxidation barrier wetting surface for solder paste. UBM stacking is very important to reduce the stress under the IC solder joint.

As mentioned earlier, there are many types of solder bump manufacturing techniques. The evaporation method requires sputtering a barrier metal (using a mask or photolithography as an auxiliary means) on the wafer surface to form UMB, and then evaporating Sn and Pb to form solder. The Sn and Pb solders are reflowed in subsequent processes to form spherical bumps. This technology is very suitable for bumps with high lead content (relative to fusible solder bumps) using high temperature resistant ceramic substrates. But for SMT applications on organic circuit boards, high-lead solder bumps on ICs also need to use fusible solder to form interconnections.

Low-cost bump fabrication technologies, such as electroplating or stencil printing (combined with sputtering or electroless UBM), are currently commonly used fabrication processes. The bump fabrication cost of these processes is lower than evaporation, and the use of fusible solder on the circuit can save the process of placing it on the circuit board and its cost. Other solder alloys currently produced include lead-free solders, high-lead solders, and low-alpha solders.

For the plating bump process, UBM material is sputtered on the entire surface of the wafer, then a photoresist is deposited, and an opening is formed in the IC bonding point by photolithography. The solder material is then plated onto the wafer and contained in the photoresist openings. Thereafter, the photoresist is peeled off, the exposed UBM material is etched, and the wafer is reflowed to form a final bump. Another commonly used method is to print a solder stencil onto a graphic UBM (sputter or electroplating) and then flow it.

Controlling the final height of the bumps is very important. It can guarantee higher assembly yield. Destructive bump cut-off test methods used to monitor bump fabrication processes often cause failure modes in the solder paste, but never cause such a result to UBM or the underlying IC solder joints.

Wafer dicing is often seen as the first step in back-end assembly. The abrasive diamond blade was sliced at 60,000 rpm. Deionized water is used in cutting to improve the quality of the cutting and extend the life of the blade. Currently, reducing chip defects on a single IC is a very urgent task. Because the chip on the top may approach the active area of the chip, the chip on the back is extremely detrimental to the reliability of the flip chip. Fractures at the edges, or even the backside chip in the chip area, often expand under the effects of thermal and mechanical stress, leading to early failure of the device.

Flux pick-up and reflow

After the wafer is diced, the diced individual chips can be left on the wafer or placed in a waffle packaging container, gel container, Surftape, or tape and shaft package. Flip-chip layout equipment must have the ability to handle bumped chips. Waffle containers are suitable for small batches, or for test-free chips; belts and shafts are suitable for SMT placement equipment; wafers sent to placement equipment are more common, and are most suitable for high-volume manufacturing applications.

The actual flip-chip assembly process begins with dispensing flux. There are many ways to dispense flux, including immersion, extrusion coating, stencil printing, or spray coating. Each method has its advantages and scope of application. Mounting equipment is usually filled with solder or adhesive to wet the components. This method has the advantage of fixing the solder to the chip bumps.

Controlling the height of the flux film and the rotation speed of the disk is necessary for repeatability in mass production. The flux distribution process must precisely control the flux distribution and repeatability. Stencil printing flux is suitable for mass production, but has higher requirements for countercurrent equipment. No matter which method is used, the characteristics of the material and the compatibility of the flux used must be considered when attaching the flip-chip device.

After the flux distribution process is completed, the chip can be picked up using a multi-head high-speed component pick-up system or an ultra-high-precision pick-and-place system. To promote the integration of semiconductor back-end manufacturing and the EMS assembly market.