What Is a Boundary Scan?

The Boundary Scan test was developed in the 1990s. With the advent of large-scale integrated circuits, printed circuit board manufacturing processes have evolved to small, micro, and thin. Traditional ICT testing has been unable to meet the requirements of this type of products. Testing requirements. Because the chip has many pins, the components are small, and the density of the board is particularly large, there is no way to test the probe. A new test technology has emerged. The Joint Test Action Group (JTAG), for short, defines this new test method as boundary scan testing.

In modern electronic application systems, the design of printed circuit boards is becoming more and more complicated. The design of multilayer boards is becoming more and more common. A large number of surface-mount components and B GA (ball grid array) package components are used. Pin density is constantly increasing, and traditional probe methods for testing chips with multimeters and oscilloscopes have been unable to meet the requirements. In this context, as early as the 1980s, the Joint Test Action Group (JTA G) drafted the boundary2scan testing (BST) specification, which was later approved as an IEEE standard in 1990. 1149. 121990 provides the JTAG standard for short. The standard specifies the hardware and software required for boundary scan testing. Since its approval in 1990, the IEEE supplemented the standard in 1993 and 1995, respectively, forming the IEEE1149.1a-1993 and IEEE1149.1b-1994, which are currently used. JTAG is mainly used in: circuit's boundary scan test and programmable chip online
1990
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Boundary scan test is performed by attaching a boundary scan unit to each I / O pin of the chip
(BSC, boundary scan cell) and some additional test control logic, BSC is mainly composed of registers. Each I / O pin has a BSC, and each BSC has two data channels: one is a test data channel, test data input TDI (test data input), test data output TDO (test data output); the other is Normal data channel: normal data input (NDI) and normal data output (NDO).
In normal working state, input and output data can pass freely through each BSC, and normal working data comes in from NDI and comes out from NDO. In the test state, you can choose the channel through which data flows: for input IC (integrated circuit) pins, you can choose to input data from NDI or from TDI; for output IC pins, you can choose to output data from BSC to NDO You can also choose to output data from BSC to TDO.
In order to test the connection of two JTAG devices, first set the BSC of an output test pin of JTAG device 1 to high or low level and output it to NDO. Then, let the input test pin of JTAG device 2 capture the input from the pin NDI value, and then output the captured data to TDO through the test data channel. By comparing the test results, you can quickly and accurately determine whether these two pins are connected reliably.
The IEEE 1149.1 standard specifies a four-wire serial interface (the fifth line is optional). This interface is called a test access port (TAP) and is used to access complex integrated circuits (ICs) such as microprocessors, DSPs , ASIC and CPLD. In addition to TAP, hybrid ICs also include shift registers and state machines to perform boundary-scan functions. The data entered into the chip on the TDI (test data input) leads is stored in the instruction register or a data register. Serial data leaves the chip from the TDO (Test Data Output) lead. The boundary scan logic is clocked by a signal on the TCK (test clock), and the TMS (test mode selection) signal drives the state of the TAP controller. TRST (Test Reset) is optional. Multiple ICs compatible with scan functions can be serially interconnected on the PCB to form one or more scan chains, each of which has its own TAP. Each scan chain provides electrical access from the serial TAP interface to every lead on every IC that is part of the chain. During normal operation, the IC performs its intended function as if the boundary scan circuit does not exist. However, when the device's scan logic is activated for testing or in-system programming, data can be transferred to the IC and read out from the IC using a serial interface. This data can be used to activate the device core, send signals from the device leads to the PCB, read out the input leads of the PCB and read out the device output [3] .

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