What Is an IP Core?

IP core is the meaning of intellectual property core or intellectual property module, which has a very important position in the development of EDA technology. The well-known American Dataquest consulting company defines the IP of the semiconductor industry as "pre-designed circuit function modules used in ASIC or FPGA". IP is mainly divided into soft IP, solid IP and hard IP. Soft IP is a functional block described in a hardware description language such as Verilog / VHDL, but it does not involve any specific circuit elements to achieve these functions. Solid IP is a functional block that completes the synthesis. Hard IP provides the final product of the designmask. ^[1]

The IP (Intellectual Property) core will be some commonly used but complex functional blocks in digital circuits, such as

IP core has three different forms of existence: HDL language form, netlist form, layout form. Corresponds to the three types of IP cores we often say:

Digital-to-analog converter (DACS) converts a binary number into a corresponding voltage value. Commonly used

Program written in VHDL language

  library ieee;
 use ieeestd_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 entity dac_ds is
 port (reset: in std_logic;
 clk: in std_logic;
 din: in std_logic_vector (7 downto 0);-Signed integer
 dout: out std_logic;
 );
 end dac_ds;
 architecture arch_dac_ds of dac_ds is
 signal error: std_logic_vector (9 downto 0);-Error accumulator is 2 bits larger
 constant zeros: std_logic_vector (7 downto 0): = (others => '0');
 begin
 process (reset, clk, din)
 variable val: std_logic_vector (9 downto 0);
 begin
 if reset = '1'then
 error <= (others => '0');
 dout <= '0';
 elsif clk'event and clk = '1' then
 --val: = din + error; din is sign extended to nbits + 2
 val: = (din (din'high) & din (din'high) & din) + error;
 if val (val'high) = '0'then
 dout <= '1';
 error <= val + ("11" & zeros);
 else
 dout <= '0';
 error <= val + ("01" & zeros);
 end if;
 end if;
 end process;
 end arch_dac_ds;

Intellectual property (IP) reuse is the main strategy for design teams to win rapid time to market because it is left to designers to complete

IP core certification

Certification can determine whether the IP block meets the relevant reuse standards. It provides a measure of the quality of block reuse and should be completed before the IP enters the resource base. Since the IP creator is familiar with IP, he should test the consistency between block concepts and compatibility with tools, libraries, and hardware platforms. An independent certification team predicts the quality and reliability of the IP core through random sampling of deliverability, reuse, and error history to determine the classification level of the IP. This level allows designers to have a general concept, such as how good the IP is in compliance with the standard, and how much soft plug work is required before using it.

IP core integration optimization

To reuse the IP core, the creator needs to soft-plug the IP, authenticate it, and store it in a resource library accessible to the system designer. Automation tools provide multiple means to accelerate the operation of soft plugs and resource libraries, and to partially automate the certification and integration process. Tool manufacturers strive for more automation. Ideally, all IP blocks can be supplied on demand from the resource library.

Accelerated IP core cycle

Designers have little ability to develop new products that meet specifications within a three-month design cycle. If a design platform is established for each product family, the design team can give full play to the role of the platform and develop derivative products of the product. An effective reuse approach should allow the development of reusable IP as part of the platform and quickly integrate IP blocks into derivatives.

IP core infrastructure

Once IP becomes widely available, support for that IP is necessary. The founders continue to own the IP because supporting it requires deep knowledge. The creator is responsible for updating the IP and placing the latest version in the repository. IP is recertified by a certification group serving system designers. In addition, the creator should provide the necessary support when the system designer encounters difficulties in integrating IP. ^[1]