What Is a Control Break?

Multiple external interrupt sources share interrupt resources, and corresponding problems must be solved, for example, there is only one INTR input on the CPU chip, how multiple interrupt sources are connected to the INTR, how interrupt vectors are distinguished, and how each interrupt source is determined. The programmable interrupt controller 8259A is designed for this purpose. It can receive interrupt requests from multiple external interrupt sources and perform priority judgment. The interrupt request with the highest priority is selected, and this request is sent to the INTR of the CPU. end. After the CPU responds to the interrupt and enters the processing of the interrupt service routine, the interrupt controller is still responsible for the management of external interrupt requests.

Multiple external

8259A External pin signal of interrupt controller 8259A

The 8259A is manufactured using NMOS technology and uses a single 5V power supply. It is a dual in-line chip with 28 pins. The functions of the external pins, except for power and ground, are as follows:

: Two-way data line, three-state, directly connected to the system data bus to achieve data exchange with the CPU. In larger systems, it is generally connected to the system data bus via a bus driver.

: External interrupt request signal input. The interrupt request signal can be level-triggered or edge-triggered, which is determined by programming. 8-level interrupt request signal input pin. When there are multiple 8259A cascades, the INT of the slave is connected to the master.

In the 8088 system, the data bus is 8 bits, and the data of 8259A is also 8 bits.

Connected directly to 8259A

You can assign an odd address and an even address to the 8259A, so as to meet the requirements for the port address when programming the 8259A.

8259A Internal structure of interrupt controller 8259A

The internal structure of 8259A consists of the following parts:

(1) Data bus buffer. It is an 8-bit bidirectional tri-state buffer, which is usually connected to the lower 8 bits of the data bus. It is the interface for data exchange between the 8259A and the CPU. The data exchanged includes the data that the 8259A inputs to the CPU, status information, and the data that the CPU sends to the 8259A. , Command, and control word all go through the data bus buffer.

(2) Read / write control circuit. It is used to receive the read and write commands, chip select signals, and port select signals sent by the CPU to implement the CPU's read / write operations on the 8259A. The signal is valid when the CPU executes the OUT instruction.

(3) Cascade buffer / comparator. A piece of 8259A can only receive 8 levels of interrupt input. When it exceeds 8 levels, multiple pieces can be cascaded to form an interrupt system with a master-slave relationship.

(4) Interrupt request register IRR. Interrupt request register IRR is used to store the interrupt request signal of external input.

(5) Interrupt mask register IMR. IMR is an 8-bit register used to store masking information for interrupt requests at all levels.

(6) Interrupt server register ISR. ISR is an 8-bit register that corresponds to 8-level interrupts and is used to record interrupt requests that are being processed.

(7) Priority disc discriminator PR. Used to manage and identify the priority level of each interrupt request signal.

(8) Control circuit. It is the internal controller of the 8259A, which controls the internal working process of the 8259A chip. ^[2]