What Are the Different Types of Time Clock Systems?

It is mainly used in the fields that require a uniform time for production and dispatching units such as: electricity, airports, light rail, subways, stadiums, hotels, hospitals, military units, oil fields, hydraulic engineering and other fields. The large-area clock system is mainly composed of a master clock and multiple clocks.

Clock system

Right!

It is mainly used in the fields that require a uniform time for production and dispatching units such as: electricity, airports, light rail, subways, stadiums, hotels, hospitals, military units, oil fields, hydraulic engineering and other fields. The large-area clock system is mainly composed of a master clock and multiple clocks.

Chinese name

Clock system

Loop structure

External 25MHz reference clock signal

Loop formation

Phase detector, filter

Simulation results

Have better linearity

High-performance processor clock system based on CMOS process, integrated

The entire loop includes modules such as phase detectors, filters, voltage-controlled oscillators, frequency dividers, common-mode rejection, and lock detection. The structure of the main modules is described below:

1. Phase detector VSPACE = 12 HSPACE = 12 ALT = "Figure 3: Structure of voltage controlled oscillator.

The output signal generated by the digital phase frequency detector can express the frequency and phase relative lead or lag information, and then send it to the charge pump. After the reset signal arrives, every rising edge of i triggers the "UP" signal until a rising edge of o arrives, thus ending the set state of the UP and shifting to the system reset state. Similarly, if the rising edge of o arrives before i, "DOWN" is set until a rising edge of i arrives, and then it returns to the reset state. Unless the phase and frequency of the two inputs are very close, that is, into the so-called "phase detection dead zone", the width of the pulse is generally proportional to the phase difference between the two inputs. The phase detector structure is shown in Figure 2.

Voltage controlled oscillator

The voltage-controlled oscillator is a key component in the phase-locked loop. There are many structures in practical applications. Figure 3 is a commonly used structure. The D delay unit is a key component of the entire loop, and the selection unit M is responsible for selecting different data channels.

As can be seen from Figure 3, the entire voltage controlled oscillator is based on a ring oscillator with an internal delay unit. Compared with sink-current and current-modulation voltage-controlled oscillators, this type of differential ring oscillator is widely used in chip clock generation circuits. At the same time, voltage-controlled oscillators with built-in delay units have relatively low VCO gains. Therefore, it is very suitable for the implementation of differential control and circuits on the signal path. Experiments show that the "jitter" of an oscillator with a low-gain built-in delay unit is significantly smaller than a high-gain loop, because noise is easily decoupled in a low-gain structure. The operating frequency of the oscillator's built-in delay link is generally limited. To ensure the monotonicity of the loop, the ratio of the upper and lower limits must be less than 2: 1, but it can also be determined by selecting the appropriate divider scaling factor or the VCO signal. Add programming capabilities on the path to effectively increase its operating frequency range. VSPACE = 12 HSPACE = 12 ALT = "Figure 4: Noise curve of VCO.

The frequency range of the voltage-controlled oscillator depends on the longest and shortest delays on the path. As shown in Figure 3, the outer dashed box indicates the route of the maximum frequency fh. It passes through three delay units D and one selection unit M, and the inner dashed line The box represents the route of the minimum frequency fl, and its path includes 6 delay units D and a selection unit M. The selection of different units will affect the gain of the voltage controlled oscillator and the center frequency of the loop at the same time. The frequency range can be determined separately by using multiple switches to select different delay paths, so that the frequency range of the VCO can be adjusted very flexibly, far exceeding the frequency range determined by the VCO gain.

The delay unit and selection unit can be built on the basis of a PMOS-type source-coupled differential amplifier with an NMOS-type load. It can also achieve voltage-controlled swing adjustment, mainly by adjusting the voltage and changing the effective load line. The high-impedance state of the current source increases the power supply noise suppression of the source coupling components. At the same time, the N-well also effectively isolates a large amount of noise on the P-type substrate, increasing the system noise suppression performance.

Simulation results

SpectreRF in Cadence was used to simulate the designed circuit, using 0.6m, 3V / 5V, Double Poly, Double Metal CMOS process parameters. VCO is a key module in the phase-locked loop. PSS and PNoise analysis of the VCO can obtain its phase noise graph. As shown in Figure 4, the phase noise at 100kHz is approximately -110dBc / Hz. Figure 5 is the gain curve of the VCO. The gain is about 380MHz / V, which has good linearity.

Design summary

Because the phase-locked loop contains analog circuits, noise interference is also a problem to be overcome in the design. Power supply noise generated by large digital circuit inversion affects the operation of analog circuits in the phase-locked loop. The clock cycle of the output will change due to the influence of power supply noise or other interference sources (such as the thermal noise of MOS tubes). It is usually called The output "dithers". Clock jitter will directly affect the highest operating frequency of the integrated circuit because it will reduce the available clock cycles. As available clock cycles decrease, digital circuits on the critical path do not get long enough to process data in one cycle, directly leading to the so-called "critical path error." In addition, when there is high-power chip interference or digital-analog mixed circuit common substrate, the influence of power supply noise is more obvious. VSPACE = 12 HSPACE = 12 ALT = "Figure 5: VCO gain curve.

The frequency deviation fout and phase deviation out caused by a noise source with a frequency of fm at the output can be expressed as

out =

The performance of high-frequency noise and low-frequency noise is very different due to different generation mechanisms, so the suppression methods adopted for different applications are different. Low-frequency noise generally includes power supply ripple, random thermal noise of resistors and transistors, and random flicker noise of transistors. High-frequency noise mainly comes from high-speed flipping of digital circuits and fast switching of chip control components. In chip clock design, this type of noise dominates. Because high-frequency noise has a relatively high frequency, the phase shift out produced is relatively small. Generally, high-frequency noise is described by periodic jitter.

Classic phase-locked loops contain analog circuits, so they are very sensitive to noise. For integrated phase-locked loops, the following measures are generally used to eliminate noise:

1. Surround the entire PLL with power and ground. The ground coil can keep the substrate potential around the phase-locked loop stable, and the constant substrate potential can suppress noise. Most of the noise introduced by the input-output unit and other logic circuits is introduced through the substrate coupling.

2. Separate the power lines of the phase-locked loop from the power lines of the other systems on the chip. Because the instantaneous large current often occurs in the logic circuit section or the interface circuit section, the potential of the main power source is constantly changing. The changing power supply voltage will affect the phase-locked loop noise suppression function, so when designing the power supply and ground of the phase-locked loop, you should consider separating the main power supply part from the power supply part of the phase-locked loop, and both are given by separate pins.

3. Place the input pin of the phase-locked loop next to the phase-locked loop to prevent it from being affected by power fluctuations and other interference.